Changeset 78623bce in rtems


Ignore:
Timestamp:
Apr 8, 2010, 10:13:46 AM (10 years ago)
Author:
Thomas Doerfler <Thomas.Doerfler@…>
Branches:
4.10, 4.11, master
Children:
42fc45c6
Parents:
d38c830
Message:

add/adapt documentation

Location:
cpukit
Files:
14 edited

Legend:

Unmodified
Added
Removed
  • cpukit/ChangeLog

    rd38c830 r78623bce  
     12010-04-08      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * score/include/rtems/score/object.h: Documentation.
     4
    152010-04-07      Joel Sherrill <joel.sherrill@oarcorp.com>
    26
  • cpukit/score/cpu/arm/ChangeLog

    rd38c830 r78623bce  
     12010-04-08      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * arm_exc_abort.S, arm_exc_handler_high.c, arm_exc_handler_low.S,
     4        arm_exc_interrupt.S, cpu.c, cpu_asm.S, rtems/asm.h, rtems/score/arm.h,
     5        rtems/score/cpu.h, rtems/score/cpu_asm.h, rtems/score/types.h:
     6        Documentation.
     7
    182010-04-07      Joel Sherrill <joel.sherrill@oarcorp.com>
    29
  • cpukit/score/cpu/arm/arm_exc_abort.S

    rd38c830 r78623bce  
    22 * @file
    33 *
    4  * @ingroup arm
     4 * @ingroup ScoreCPU
    55 *
    66 * @brief ARM data and prefetch abort exception prologue and epilogue.
  • cpukit/score/cpu/arm/arm_exc_handler_high.c

    rd38c830 r78623bce  
    22 * @file
    33 *
    4  * ARM exception support code.
     4 * @ingroup ScoreCPU
     5 *
     6 * @brief ARM exception support implementation.
    57 */
    68
  • cpukit/score/cpu/arm/arm_exc_handler_low.S

    rd38c830 r78623bce  
    22 * @file
    33 *
    4  * ARM exception support code.
     4 * @ingroup ScoreCPU
     5 *
     6 * @brief ARM exception support implementation.
    57 */
    68
  • cpukit/score/cpu/arm/arm_exc_interrupt.S

    rd38c830 r78623bce  
    22 * @file
    33 *
    4  * @ingroup arm
     4 * @ingroup ScoreCPU
    55 *
    66 * @brief ARM interrupt exception prologue and epilogue.
  • cpukit/score/cpu/arm/cpu.c

    rd38c830 r78623bce  
    22 * @file
    33 *
    4  * ARM support code.
     4 * @ingroup ScoreCPU
     5 *
     6 * @brief ARM architecture support implementation.
    57 */
    68
  • cpukit/score/cpu/arm/cpu_asm.S

    rd38c830 r78623bce  
     1/**
     2 * @file
     3 *
     4 * @ingroup ScoreCPU
     5 *
     6 * @brief ARM architecture support implementation.
     7 */
     8
    19/*
    210 *  $Id$
  • cpukit/score/cpu/arm/rtems/asm.h

    rd38c830 r78623bce  
    11/**
    2  * @file rtems/asm.h
     2 * @file
    33 *
     4 * @ingroup ScoreCPU
     5 *
     6 * @brief ARM assembler support API.
     7 */
     8
     9/*
    410 *  This include file attempts to address the problems
    511 *  caused by incompatible flavors of assemblers and
     
    4248#include <rtems/score/cpuopts.h>
    4349#include <rtems/score/arm.h>
     50
     51/**
     52 * @defgroup ScoreCPUARMASM ARM Assembler Support
     53 *
     54 * @ingroup ScoreCPU
     55 *
     56 * @brief ARM assembler support.
     57 *
     58 * @{
     59 */
    4460
    4561/*
     
    158174.endm
    159175
     176/** @} */
     177
    160178#endif /* _RTEMS_ASM_H */
  • cpukit/score/cpu/arm/rtems/score/arm.h

    rd38c830 r78623bce  
    11/**
    2  * @file rtems/score/arm.h
     2 * @file
     3 *
     4 * @ingroup ScoreCPU
     5 *
     6 * @brief ARM assembler support API.
    37 */
    48
     
    2428extern "C" {
    2529#endif
     30
     31/**
     32 * @addtogroup ScoreCPU
     33 *
     34 * @{
     35 */
    2636
    2737/*
     
    8090#define CPU_NAME "ARM"
    8191
     92/** @} */
     93
    8294#ifdef __cplusplus
    8395}
  • cpukit/score/cpu/arm/rtems/score/cpu.h

    rd38c830 r78623bce  
    11/**
    2  * @file rtems/score/cpu.h
     2 * @file
     3 *
     4 * @ingroup ScoreCPU
     5 *
     6 * @brief ARM architecture support API.
    37 */
    48
     
    4549  #define FALSE 0
    4650#endif
     51
     52/**
     53 * @defgroup ScoreCPUARM ARM Specific Support
     54 *
     55 * @ingroup ScoreCPU
     56 *
     57 * @brief ARM specific support.
     58 *
     59 * @{
     60 */
    4761
    4862#ifdef __thumb__
     
    5973  #define ARM_SWITCH_ADDITIONAL_OUTPUT
    6074#endif
     75
     76/**
     77 * @name Program Status Register
     78 *
     79 * @{
     80 */
    6181
    6282#define ARM_PSR_N (1 << 31)
     
    83103#define ARM_PSR_M_SYS 0x1f
    84104
     105/** @} */
     106
     107/** @} */
     108
     109/**
     110 * @addtogroup ScoreCPU
     111 *
     112 * @{
     113 */
     114
    85115/* If someone uses THUMB we assume she wants minimal code size */
    86116#ifdef __thumb__
     
    184214#define CPU_ENABLE_C_ISR_DISPATCH_IMPLEMENTATION TRUE
    185215
     216/** @} */
     217
    186218#ifndef ASM
    187219
     
    190222#endif
    191223
    192 typedef enum {
    193   ARM_EXCEPTION_RESET = 0,
    194   ARM_EXCEPTION_UNDEF = 1,
    195   ARM_EXCEPTION_SWI = 2,
    196   ARM_EXCEPTION_PREF_ABORT = 3,
    197   ARM_EXCEPTION_DATA_ABORT = 4,
    198   ARM_EXCEPTION_RESERVED = 5,
    199   ARM_EXCEPTION_IRQ = 6,
    200   ARM_EXCEPTION_FIQ = 7,
    201   MAX_EXCEPTIONS = 8
    202 } Arm_symbolic_exception_name;
     224/**
     225 * @addtogroup ScoreCPU
     226 *
     227 * @{
     228 */
    203229
    204230typedef struct {
     
    217243} Context_Control;
    218244
    219 /* XXX This is out of date */
    220 typedef struct {
    221   uint32_t register_r0;
    222   uint32_t register_r1;
    223   uint32_t register_r2;
    224   uint32_t register_r3;
    225   uint32_t register_ip;
    226   uint32_t register_lr;
    227 } CPU_Exception_frame;
    228 
    229 typedef CPU_Exception_frame CPU_Interrupt_frame;
    230 
    231245typedef struct {
    232246  /* Not supported */
     
    234248
    235249SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
     250
     251extern uint32_t arm_cpu_mode;
    236252
    237253static inline uint32_t arm_interrupt_disable( void )
     
    278294    : [level] "r" (level)
    279295  );
    280 }
    281 
    282 static inline uint32_t arm_status_irq_enable( void )
    283 {
    284   uint32_t arm_switch_reg;
    285   uint32_t psr;
    286 
    287   RTEMS_COMPILER_MEMORY_BARRIER();
    288 
    289   asm volatile (
    290     ARM_SWITCH_TO_ARM
    291     "mrs %[psr], cpsr\n"
    292     "bic %[arm_switch_reg], %[psr], #0x80\n"
    293     "msr cpsr, %[arm_switch_reg]\n"
    294     ARM_SWITCH_BACK
    295     : [arm_switch_reg] "=&r" (arm_switch_reg), [psr] "=&r" (psr)
    296   );
    297 
    298   return psr;
    299 }
    300 
    301 static inline void arm_status_restore( uint32_t psr )
    302 {
    303   ARM_SWITCH_REGISTERS;
    304 
    305   asm volatile (
    306     ARM_SWITCH_TO_ARM
    307     "msr cpsr, %[psr]\n"
    308     ARM_SWITCH_BACK
    309     : ARM_SWITCH_OUTPUT
    310     : [psr] "r" (psr)
    311   );
    312 
    313   RTEMS_COMPILER_MEMORY_BARRIER();
    314296}
    315297
     
    414396}
    415397
    416 /* XXX */
    417 
    418 extern uint32_t arm_cpu_mode;
     398/** @} */
     399
     400/**
     401 * @addtogroup ScoreCPUARM
     402 *
     403 * @{
     404 */
    419405
    420406typedef struct {
     
    440426typedef void arm_exc_abort_handler( arm_cpu_context *context );
    441427
     428typedef enum {
     429  ARM_EXCEPTION_RESET = 0,
     430  ARM_EXCEPTION_UNDEF = 1,
     431  ARM_EXCEPTION_SWI = 2,
     432  ARM_EXCEPTION_PREF_ABORT = 3,
     433  ARM_EXCEPTION_DATA_ABORT = 4,
     434  ARM_EXCEPTION_RESERVED = 5,
     435  ARM_EXCEPTION_IRQ = 6,
     436  ARM_EXCEPTION_FIQ = 7,
     437  MAX_EXCEPTIONS = 8
     438} Arm_symbolic_exception_name;
     439
     440static inline uint32_t arm_status_irq_enable( void )
     441{
     442  uint32_t arm_switch_reg;
     443  uint32_t psr;
     444
     445  RTEMS_COMPILER_MEMORY_BARRIER();
     446
     447  asm volatile (
     448    ARM_SWITCH_TO_ARM
     449    "mrs %[psr], cpsr\n"
     450    "bic %[arm_switch_reg], %[psr], #0x80\n"
     451    "msr cpsr, %[arm_switch_reg]\n"
     452    ARM_SWITCH_BACK
     453    : [arm_switch_reg] "=&r" (arm_switch_reg), [psr] "=&r" (psr)
     454  );
     455
     456  return psr;
     457}
     458
     459static inline void arm_status_restore( uint32_t psr )
     460{
     461  ARM_SWITCH_REGISTERS;
     462
     463  asm volatile (
     464    ARM_SWITCH_TO_ARM
     465    "msr cpsr, %[psr]\n"
     466    ARM_SWITCH_BACK
     467    : ARM_SWITCH_OUTPUT
     468    : [psr] "r" (psr)
     469  );
     470
     471  RTEMS_COMPILER_MEMORY_BARRIER();
     472}
     473
    442474void arm_exc_data_abort_set_handler( arm_exc_abort_handler handler );
    443475
     
    454486void arm_exc_undefined( void );
    455487
     488/** @} */
     489
     490/* XXX This is out of date */
     491typedef struct {
     492  uint32_t register_r0;
     493  uint32_t register_r1;
     494  uint32_t register_r2;
     495  uint32_t register_r3;
     496  uint32_t register_ip;
     497  uint32_t register_lr;
     498} CPU_Exception_frame;
     499
     500typedef CPU_Exception_frame CPU_Interrupt_frame;
     501
    456502#ifdef __cplusplus
    457503}
  • cpukit/score/cpu/arm/rtems/score/cpu_asm.h

    rd38c830 r78623bce  
    11/**
    2  * @file rtems/score/cpu_asm.h
     2 * @file
     3 *
     4 * @ingroup ScoreCPU
     5 *
     6 * @brief ARM assembler support API.
    37 */
    48
  • cpukit/score/cpu/arm/rtems/score/types.h

    rd38c830 r78623bce  
    11/**
    2  * @file rtems/score/types.h
     2 * @file
     3 *
     4 * @ingroup ScoreCPU
     5 *
     6 * @brief ARM architecture types API.
    37 */
    48
     
    3034#endif
    3135
     36/**
     37 * @addtogroup ScoreCPU
     38 *
     39 * @{
     40 */
     41
    3242/*
    3343 *  This section defines the basic types for this processor.
     
    4252#endif
    4353
     54/** @} */
     55
    4456#ifdef __cplusplus
    4557}
  • cpukit/score/include/rtems/score/object.h

    rd38c830 r78623bce  
    3838 *
    3939 * @brief Provides services for all APIs.
     40 */
     41
     42/**
     43 * @defgroup ScoreCPU CPU Architecture Support
     44 *
     45 * @ingroup Score
     46 *
     47 * @brief Provides CPU architecture dependent services.
    4048 */
    4149
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