Changeset 783e8322 in rtems
- Timestamp:
- 08/03/99 13:52:59 (24 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- a1c70a2
- Parents:
- 26eff5c
- Location:
- c/src/lib/libbsp/i386
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/i386/pc386/startup/ldsegs.S
r26eff5c r783e8322 140 140 call SYM(delay) 141 141 142 movw $0xFFFB, SYM(i8259s_cache) /* set up same values in cache */143 144 142 jmp SYM (_establish_stack) # return to the bsp entry code 145 143 -
c/src/lib/libbsp/i386/shared/irq/irq.c
r26eff5c r783e8322 54 54 * This cache is initialized in ldseg.s 55 55 */ 56 rtems_i8259_masks i8259s_cache ;56 rtems_i8259_masks i8259s_cache = 0xffbf; 57 57 58 58 /*-------------------------------------------------------------------------+ … … 84 84 else 85 85 { 86 outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) > 8));86 outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); 87 87 } 88 88 _CPU_ISR_Enable (level); … … 119 119 else 120 120 { 121 outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) > 8));121 outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); 122 122 } 123 123 _CPU_ISR_Enable (level);
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