Changeset 783e8322 in rtems


Ignore:
Timestamp:
08/03/99 13:52:59 (24 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
a1c70a2
Parents:
26eff5c
Message:

Patch from Eric Valette <valette@…> to fix interrupt
initialization typo and make i8259s_cache only accessed from C.

Location:
c/src/lib/libbsp/i386
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • c/src/lib/libbsp/i386/pc386/startup/ldsegs.S

    r26eff5c r783e8322  
    140140        call    SYM(delay)
    141141
    142         movw    $0xFFFB, SYM(i8259s_cache) /* set up same values in cache */
    143        
    144142        jmp     SYM (_establish_stack)  # return to the bsp entry code
    145143

  • c/src/lib/libbsp/i386/shared/irq/irq.c

    r26eff5c r783e8322  
    5454 * This cache is initialized in ldseg.s
    5555 */
    56 rtems_i8259_masks i8259s_cache;
     56rtems_i8259_masks i8259s_cache = 0xffbf;
    5757
    5858/*-------------------------------------------------------------------------+
    … …  
    8484  else
    8585  {
    86     outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) > 8));
     86    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
    8787  }
    8888  _CPU_ISR_Enable (level);
    … …  
    119119  else
    120120  {
    121     outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) > 8));
     121    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
    122122  }
    123123  _CPU_ISR_Enable (level);
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