Changeset 77f9a1b in rtems


Ignore:
Timestamp:
Apr 10, 2019, 11:38:55 PM (2 months ago)
Author:
Jeff Kubascik <jeff.kubascik@…>
Branches:
master
Children:
cfcd6dc9
Parents:
677d5167
git-author:
Jeff Kubascik <jeff.kubascik@…> (04/10/19 23:38:55)
git-committer:
Sebastian Huber <sebastian.huber@…> (04/11/19 05:29:10)
Message:

bsp/xilinx-zynqmp: Implement Ultra96 target

Modifications to get xilinx-zynqmp BSP working on an Ultra96 board.

Update #3682.

Files:
1 added
15 edited
1 moved

Legend:

Unmodified
Added
Removed
  • bsps/arm/xilinx-zynqmp/README

    r677d5167 r77f9a1b  
    1 Tested only on Qemu.
     1Tested on an Ultra96 board with JTAG boot.
    22
    3 git clone git://git.qemu.org/qemu.git qemu
    4 cd qemu
    5 git checkout 1b0d3845b454eaaac0b2064c78926ca4d739a080
    6 mkdir build
    7 cd build
    8 ../configure --prefix=/opt/qemu --interp-prefix=/opt/qemu
    9 make
    10 make install
    11 export PATH="$PATH:/opt/qemu/bin"
     3Make sure to configure the boot mode switches for JTAG mode.
    124
    13 qemu-system-arm -no-reboot -serial null -serial mon:stdio -net none -nographic -M xilinx-zynq-a9 -m 256M -kernel ticker.exe
     5Using the xsct tool, load and run the application with
     6
     7connect
     8
     9targets -set -filter {name =~ "PSU"}
     10rst -system
     11source psu_init.tcl
     12psu_init
     13
     14targets -set -filter {name =~ "Cortex-A53 #0"}
     15rst -processor
     16dow ticker.exe
     17
     18# Set generic timer frequency
     19rwr sys 14 cntfrq_el0 100000000
     20
     21# Switch to AArch32 Supervisor mode
     22rwr cpsr 0x2001d3
     23
     24# Boot arguments
     25rwr r0 0
     26rwr r1 0
     27rwr r2 0
     28rwr r3 0
     29
     30con
  • bsps/arm/xilinx-zynqmp/config/xilinx_zynqmp.inc

    r677d5167 r77f9a1b  
    33RTEMS_CPU = arm
    44
    5 CPU_CFLAGS = -march=armv7-a -mthumb -mfpu=neon -mfloat-abi=hard -mtune=cortex-a9
     5CPU_CFLAGS = -march=armv7-a -mthumb -mfpu=neon -mfloat-abi=hard -mtune=cortex-a53
    66
    77CFLAGS_OPTIMIZE_V ?= -O2 -g
  • bsps/arm/xilinx-zynqmp/console/console-config.c

    r677d5167 r77f9a1b  
    33 *
    44 * Copyright (C) 2013, 2017 embedded brains GmbH
     5 *
     6 * Copyright (C) 2019 DornerWorks
     7 *
     8 * Written by Jeff Kubascik <jeff.kubascik@dornerworks.com>
     9 *        and Josh Whitehead <josh.whitehead@dornerworks.com>
    510 *
    611 * Redistribution and use in source and binary forms, with or without
     
    2833#include <rtems/console.h>
    2934#include <rtems/bspIo.h>
     35#include <rtems/sysinit.h>
    3036
    3137#include <bsp/irq.h>
     
    3440#include <bspopts.h>
    3541
    36 zynq_uart_context zynq_uart_instances[2] = {
     42static zynq_uart_context zynqmp_uart_instances[2] = {
    3743  {
    3844    .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ),
    39     .regs = (volatile struct zynq_uart *) 0xe0000000,
    40     .irq = ZYNQ_IRQ_UART_0
     45    .regs = (volatile struct zynq_uart *) 0xff000000,
     46    .irq = ZYNQMP_IRQ_UART_0
    4147  }, {
    4248    .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 1" ),
    43     .regs = (volatile struct zynq_uart *) 0xe0001000,
    44     .irq = ZYNQ_IRQ_UART_1
     49    .regs = (volatile struct zynq_uart *) 0xff010000,
     50    .irq = ZYNQMP_IRQ_UART_1
    4551  }
    4652};
     
    5662  rtems_termios_initialize();
    5763
    58   for (i = 0; i < RTEMS_ARRAY_SIZE(zynq_uart_instances); ++i) {
     64  for (i = 0; i < RTEMS_ARRAY_SIZE(zynqmp_uart_instances); ++i) {
    5965    char uart[] = "/dev/ttySX";
    6066
     
    6470      &zynq_uart_handler,
    6571      NULL,
    66       &zynq_uart_instances[i].base
     72      &zynqmp_uart_instances[i].base
    6773    );
    6874
     
    7480  return RTEMS_SUCCESSFUL;
    7581}
     82
     83void zynqmp_debug_console_flush(void)
     84{
     85  zynq_uart_reset_tx_flush(&zynqmp_uart_instances[BSP_CONSOLE_MINOR]);
     86}
     87
     88static void zynqmp_debug_console_out(char c)
     89{
     90  rtems_termios_device_context *base =
     91    &zynqmp_uart_instances[BSP_CONSOLE_MINOR].base;
     92
     93  zynq_uart_write_polled(base, c);
     94}
     95
     96static void zynqmp_debug_console_init(void)
     97{
     98  rtems_termios_device_context *base =
     99    &zynqmp_uart_instances[BSP_CONSOLE_MINOR].base;
     100
     101  zynq_uart_initialize(base);
     102  BSP_output_char = zynqmp_debug_console_out;
     103}
     104
     105static void zynqmp_debug_console_early_init(char c)
     106{
     107  rtems_termios_device_context *base =
     108    &zynqmp_uart_instances[BSP_CONSOLE_MINOR].base;
     109
     110  zynq_uart_initialize(base);
     111  zynqmp_debug_console_out(c);
     112}
     113
     114static int zynqmp_debug_console_in(void)
     115{
     116  rtems_termios_device_context *base =
     117    &zynqmp_uart_instances[BSP_CONSOLE_MINOR].base;
     118
     119  return zynq_uart_read_polled(base);
     120}
     121
     122BSP_output_char_function_type BSP_output_char = zynqmp_debug_console_early_init;
     123
     124BSP_polling_getchar_function_type BSP_poll_char = zynqmp_debug_console_in;
     125
     126RTEMS_SYSINIT_ITEM(
     127  zynqmp_debug_console_init,
     128  RTEMS_SYSINIT_BSP_START,
     129  RTEMS_SYSINIT_ORDER_LAST
     130);
  • bsps/arm/xilinx-zynqmp/headers.am

    r677d5167 r77f9a1b  
    22
    33include_HEADERS =
    4 include_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp.h
     4include_HEADERS += ../../../../../../bsps/arm/xilinx-zynqmp/include/bsp.h
    55include_HEADERS += include/bspopts.h
    6 include_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/tm27.h
     6include_HEADERS += ../../../../../../bsps/arm/xilinx-zynqmp/include/tm27.h
    77
    88include_bspdir = $(includedir)/bsp
    99include_bsp_HEADERS =
    10 include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h
    11 include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h
    12 include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/i2c.h
    13 include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/irq.h
    14 include_bsp_HEADERS += ../../../../../../bsps/arm/include/bsp/zynq-uart-regs.h
    15 include_bsp_HEADERS += ../../../../../../bsps/arm/include/bsp/zynq-uart.h
     10include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynqmp/include/bsp/irq.h
  • bsps/arm/xilinx-zynqmp/include/bsp.h

    r677d5167 r77f9a1b  
    11/**
    22 * @file
    3  * @ingroup RTEMSBSPsARMZynq
     3 * @ingroup RTEMSBSPsARMZynqMP
    44 * @brief Global BSP definitions.
    55 */
     
    99 *
    1010 * Copyright (C) 2013, 2014 embedded brains GmbH
     11 *
     12 * Copyright (C) 2019 DornerWorks
     13 *
     14 * Written by Jeff Kubascik <jeff.kubascik@dornerworks.com>
     15 *        and Josh Whitehead <josh.whitehead@dornerworks.com>
    1116 *
    1217 * Redistribution and use in source and binary forms, with or without
     
    3237 */
    3338
    34 #ifndef LIBBSP_ARM_XILINX_ZYNQ_BSP_H
    35 #define LIBBSP_ARM_XILINX_ZYNQ_BSP_H
     39#ifndef LIBBSP_ARM_XILINX_ZYNQMP_BSP_H
     40#define LIBBSP_ARM_XILINX_ZYNQMP_BSP_H
    3641
    3742/**
    38  * @defgroup RTEMSBSPsARMZynq Xilinx Zynq
     43 * @defgroup RTEMSBSPsARMZynqMP Xilinx Zynq UltraScale+ MPSoC
    3944 *
    4045 * @ingroup RTEMSBSPsARM
    4146 *
    42  * @brief Xilinx Zynq Board Support Package.
     47 * @brief Xilinx Zynq UltraScale+ MPSoC Board Support Package.
    4348 *
    4449 * @{
     
    5560#include <bsp/default-initial-extension.h>
    5661#include <bsp/start.h>
    57 #include <bsp/zynq-uart.h>
    5862
    5963#ifdef __cplusplus
     
    6165#endif /* __cplusplus */
    6266
    63 #define BSP_ARM_A9MPCORE_SCU_BASE 0xf8f00000
     67#define BSP_ARM_GIC_CPUIF_BASE 0xf9020000
    6468
    65 #define BSP_ARM_GIC_CPUIF_BASE 0xf8f00100
     69#define BSP_ARM_GIC_DIST_BASE 0xf9010000
    6670
    67 #define BSP_ARM_A9MPCORE_GT_BASE 0xf8f00200
     71#define BSP_ARM_A9MPCORE_SCU_BASE 0
    6872
    69 #define BSP_ARM_A9MPCORE_PT_BASE 0xf8f00600
    70 
    71 #define BSP_ARM_GIC_DIST_BASE 0xf8f01000
    72 
    73 #define BSP_ARM_L2C_310_BASE 0xf8f02000
    74 
    75 #define BSP_ARM_L2C_310_ID 0x410000c8
    76 
    77 extern zynq_uart_context zynq_uart_instances[2];
     73#define BSP_ARM_A9MPCORE_GT_BASE 0
    7874
    7975/**
    80  * @brief Zynq specific set up of the MMU.
     76 * @brief Zynq UltraScale+ MPSoC specific set up of the MMU.
    8177 *
    82  * Provide in the application to override
    83  * the defaults in the BSP. Note the defaults do not map in the GP0 and GP1
    84  * AXI ports. You should add the specific regions that map into your
    85  * PL rather than just open the whole of the GP[01] address space up.
     78 * Provide in the application to override the defaults in the BSP.
    8679 */
    87 BSP_START_TEXT_SECTION void zynq_setup_mmu_and_cache(void);
     80BSP_START_TEXT_SECTION void zynqmp_setup_mmu_and_cache(void);
    8881
    89 uint32_t zynq_clock_cpu_1x(void);
     82void arm_generic_timer_get_config(uint32_t *frequency, uint32_t *irq);
     83
     84void zynqmp_debug_console_flush(void);
    9085
    9186#ifdef __cplusplus
     
    9792/** @} */
    9893
    99 #endif /* LIBBSP_ARM_XILINX_ZYNQ_BSP_H */
     94#endif /* LIBBSP_ARM_XILINX_ZYNQMP_BSP_H */
  • bsps/arm/xilinx-zynqmp/include/bsp/irq.h

    r677d5167 r77f9a1b  
    11/**
    22 * @file
    3  * @ingroup zynq_interrupt
     3 * @ingroup zynqmp_interrupt
    44 * @brief Interrupt definitions.
    55 */
     
    99 *
    1010 * Copyright (C) 2013 embedded brains GmbH
     11 *
     12 * Copyright (C) 2019 DornerWorks
     13 *
     14 * Written by Jeff Kubascik <jeff.kubascik@dornerworks.com>
     15 *        and Josh Whitehead <josh.whitehead@dornerworks.com>
    1116 *
    1217 * Redistribution and use in source and binary forms, with or without
     
    3237 */
    3338
    34 #ifndef LIBBSP_ARM_XILINX_ZYNQ_IRQ_H
    35 #define LIBBSP_ARM_XILINX_ZYNQ_IRQ_H
     39#ifndef LIBBSP_ARM_XILINX_ZYNQMP_IRQ_H
     40#define LIBBSP_ARM_XILINX_ZYNQMP_IRQ_H
    3641
    3742#ifndef ASM
     
    4045#include <rtems/irq-extension.h>
    4146
    42 #include <bsp/arm-a9mpcore-irq.h>
    4347#include <bsp/arm-gic-irq.h>
    4448
     
    4852
    4953/**
    50  * @defgroup zynq_interrupt Interrupt Support
    51  * @ingroup RTEMSBSPsARMZynq
     54 * @defgroup zynqmp_interrupt Interrupt Support
     55 * @ingroup RTEMSBSPsARMZynqMP
    5256 * @brief Interrupt Support
    5357 * @{
    5458 */
    5559
    56 #define ZYNQ_IRQ_CPU_0 32
    57 #define ZYNQ_IRQ_CPU_1 33
    58 #define ZYNQ_IRQ_L2_CACHE 34
    59 #define ZYNQ_IRQ_OCM 35
    60 #define ZYNQ_IRQ_PMU_0 37
    61 #define ZYNQ_IRQ_PMU_1 38
    62 #define ZYNQ_IRQ_XADC 39
    63 #define ZYNQ_IRQ_DVI 40
    64 #define ZYNQ_IRQ_SWDT 41
    65 #define ZYNQ_IRQ_TTC_0_0 42
    66 #define ZYNQ_IRQ_TTC_1_0 43
    67 #define ZYNQ_IRQ_TTC_2_0 44
    68 #define ZYNQ_IRQ_DMAC_ABORT 45
    69 #define ZYNQ_IRQ_DMAC_0 46
    70 #define ZYNQ_IRQ_DMAC_1 47
    71 #define ZYNQ_IRQ_DMAC_2 48
    72 #define ZYNQ_IRQ_DMAC_3 49
    73 #define ZYNQ_IRQ_SMC 50
    74 #define ZYNQ_IRQ_QUAD_SPI 51
    75 #define ZYNQ_IRQ_GPIO 52
    76 #define ZYNQ_IRQ_USB_0 53
    77 #define ZYNQ_IRQ_ETHERNET_0 54
    78 #define ZYNQ_IRQ_ETHERNET_0_WAKEUP 55
    79 #define ZYNQ_IRQ_SDIO_0 56
    80 #define ZYNQ_IRQ_I2C_0 57
    81 #define ZYNQ_IRQ_SPI_0 58
    82 #define ZYNQ_IRQ_UART_0 59
    83 #define ZYNQ_IRQ_CAN_0 60
    84 #define ZYNQ_IRQ_FPGA_0 61
    85 #define ZYNQ_IRQ_FPGA_1 62
    86 #define ZYNQ_IRQ_FPGA_2 63
    87 #define ZYNQ_IRQ_FPGA_3 64
    88 #define ZYNQ_IRQ_FPGA_4 65
    89 #define ZYNQ_IRQ_FPGA_5 66
    90 #define ZYNQ_IRQ_FPGA_6 67
    91 #define ZYNQ_IRQ_FPGA_7 68
    92 #define ZYNQ_IRQ_TTC_0_1 69
    93 #define ZYNQ_IRQ_TTC_1_1 70
    94 #define ZYNQ_IRQ_TTC_2_1 71
    95 #define ZYNQ_IRQ_DMAC_4 72
    96 #define ZYNQ_IRQ_DMAC_5 73
    97 #define ZYNQ_IRQ_DMAC_6 74
    98 #define ZYNQ_IRQ_DMAC_7 75
    99 #define ZYNQ_IRQ_USB_1 76
    100 #define ZYNQ_IRQ_ETHERNET_1 77
    101 #define ZYNQ_IRQ_ETHERNET_1_WAKEUP 78
    102 #define ZYNQ_IRQ_SDIO_1 79
    103 #define ZYNQ_IRQ_I2C_1 80
    104 #define ZYNQ_IRQ_SPI_1 81
    105 #define ZYNQ_IRQ_UART_1 82
    106 #define ZYNQ_IRQ_CAN_1 83
    107 #define ZYNQ_IRQ_FPGA_8 84
    108 #define ZYNQ_IRQ_FPGA_9 85
    109 #define ZYNQ_IRQ_FPGA_10 86
    110 #define ZYNQ_IRQ_FPGA_11 87
    111 #define ZYNQ_IRQ_FPGA_12 88
    112 #define ZYNQ_IRQ_FPGA_13 89
    113 #define ZYNQ_IRQ_FPGA_14 90
    114 #define ZYNQ_IRQ_FPGA_15 91
    115 #define ZYNQ_IRQ_PARITY 92
     60/* PPIs */
     61#define ZYNQMP_IRQ_HYP_TIMER 26
     62#define ZYNQMP_IRQ_VIRT_TIMER 27
     63#define ZYNQMP_IRQ_S_PHYS_TIMER 29
     64#define ZYNQMP_IRQ_NS_PHYS_TIMER 30
     65
     66/* SPIs */
     67#define ZYNQMP_IRQ_UART_0 53
     68#define ZYNQMP_IRQ_UART_1 54
    11669
    11770#define BSP_INTERRUPT_VECTOR_MIN 0
    118 #define BSP_INTERRUPT_VECTOR_MAX 92
     71#define BSP_INTERRUPT_VECTOR_MAX 187
    11972
    12073/** @} */
     
    12679#endif /* ASM */
    12780
    128 #endif /* LIBBSP_ARM_XILINX_ZYNQ_IRQ_H */
     81#endif /* LIBBSP_ARM_XILINX_ZYNQMP_IRQ_H */
  • bsps/arm/xilinx-zynqmp/include/tm27.h

    r677d5167 r77f9a1b  
    11/**
    22 * @file
    3  * @ingroup zynq_tm27
     3 * @ingroup zynqmp_tm27
    44 * @brief Interrupt mechanisms for tm27 test.
    55 */
     
    99 *
    1010 * Copyright (C) 2013 embedded brains GmbH
     11 *
     12 * Copyright (C) 2019 DornerWorks
     13 *
     14 * Written by Jeff Kubascik <jeff.kubascik@dornerworks.com>
     15 *        and Josh Whitehead <josh.whitehead@dornerworks.com>
    1116 *
    1217 * Redistribution and use in source and binary forms, with or without
     
    4045
    4146/**
    42  * @defgroup zynq_tm27 TM27 Test Support
    43  * @ingroup RTEMSBSPsARMZynq
     47 * @defgroup zynqmp_tm27 TM27 Test Support
     48 * @ingroup RTEMSBSPsARMZynqMP
    4449 * @brief Interrupt Mechanisms for tm27 test
    4550 */
  • bsps/arm/xilinx-zynqmp/start/bspreset.c

    r677d5167 r77f9a1b  
    33 *
    44 * Copyright (C) 2013 embedded brains GmbH
     5 *
     6 * Copyright (C) 2019 DornerWorks
     7 *
     8 * Written by Jeff Kubascik <jeff.kubascik@dornerworks.com>
     9 *        and Josh Whitehead <josh.whitehead@dornerworks.com>
    510 *
    611 * Redistribution and use in source and binary forms, with or without
     
    2732
    2833#include <bsp.h>
    29 #include <bsp/bootcard.h>
    30 #include <bsp/zynq-uart.h>
    3134
    3235void bsp_reset(void)
    3336{
    34   volatile uint32_t *slcr_unlock = (volatile uint32_t *) 0xf8000008;
    35   volatile uint32_t *pss_rst_ctrl = (volatile uint32_t *) 0xf8000200;
    36 
    37   zynq_uart_reset_tx_flush(&zynq_uart_instances[BSP_CONSOLE_MINOR]);
     37  zynqmp_debug_console_flush();
    3838
    3939  while (true) {
    40     *slcr_unlock = 0xdf0d;
    41     *pss_rst_ctrl = 0x1;
     40    /* Wait */
    4241  }
    4342}
  • bsps/arm/xilinx-zynqmp/start/bspsmp.c

    r677d5167 r77f9a1b  
    33 *
    44 * Copyright (C) 2014 embedded brains GmbH
     5 *
     6 * Copyright (C) 2019 DornerWorks
     7 *
     8 * Written by Jeff Kubascik <jeff.kubascik@dornerworks.com>
     9 *        and Josh Whitehead <josh.whitehead@dornerworks.com>
    510 *
    611 * Redistribution and use in source and binary forms, with or without
  • bsps/arm/xilinx-zynqmp/start/bspstart.c

    r677d5167 r77f9a1b  
    33 *
    44 * Copyright (C) 2013, 2015 embedded brains GmbH
     5 *
     6 * Copyright (C) 2019 DornerWorks
     7 *
     8 * Written by Jeff Kubascik <jeff.kubascik@dornerworks.com>
     9 *        and Josh Whitehead <josh.whitehead@dornerworks.com>
    510 *
    611 * Redistribution and use in source and binary forms, with or without
     
    3136#include <bsp/linker-symbols.h>
    3237
    33 __attribute__ ((weak)) uint32_t zynq_clock_cpu_1x(void)
     38#include <libcpu/arm-cp15.h>
     39
     40void arm_generic_timer_get_config(uint32_t *frequency, uint32_t *irq)
    3441{
    35   return ZYNQ_CLOCK_CPU_1X;
     42#ifdef ARM_GENERIC_TIMER_FREQ
     43  *frequency = ARM_GENERIC_TIMER_FREQ;
     44#else
     45  /* Use generic timer frequency provided by boot loader */
     46  *frequency = arm_cp15_get_counter_frequency();
     47#endif
     48
     49#ifdef ARM_GENERIC_TIMER_USE_VIRTUAL
     50  *irq = ZYNQMP_IRQ_VIRT_TIMER;
     51#else
     52  *irq = ZYNQMP_IRQ_NS_PHYS_TIMER;
     53#endif
    3654}
    3755
  • bsps/arm/xilinx-zynqmp/start/bspstarthooks.c

    r677d5167 r77f9a1b  
    33 *
    44 * Copyright (C) 2013, 2014 embedded brains GmbH
     5 *
     6 * Copyright (C) 2019 DornerWorks
     7 *
     8 * Written by Jeff Kubascik <jeff.kubascik@dornerworks.com>
     9 *        and Josh Whitehead <josh.whitehead@dornerworks.com>
    510 *
    611 * Redistribution and use in source and binary forms, with or without
     
    3843
    3944  sctlr_val = arm_cp15_get_control();
     45  sctlr_val |= ARM_CP15_CTRL_CP15BEN;
     46  arm_cp15_set_control( sctlr_val );
    4047
    4148  /*
     
    7077  arm_cp15_tlb_invalidate();
    7178  arm_cp15_flush_prefetch_buffer();
    72   arm_a9mpcore_start_hook_0();
    7379}
    7480
    7581BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
    7682{
    77   arm_a9mpcore_start_hook_1();
     83  arm_a9mpcore_start_set_vector_base();
    7884  bsp_start_copy_sections();
    79   zynq_setup_mmu_and_cache();
    80 
    81 #if !defined(RTEMS_SMP) \
    82   && (defined(BSP_DATA_CACHE_ENABLED) \
    83     || defined(BSP_INSTRUCTION_CACHE_ENABLED))
    84   /* Enable unified L2 cache */
    85   rtems_cache_enable_data();
    86 #endif
    87 
     85  zynqmp_setup_mmu_and_cache();
    8886  bsp_start_clear_bss();
    8987}
  • bsps/arm/xilinx-zynqmp/start/bspstartmmu.c

    r677d5167 r77f9a1b  
    33 *
    44 * Copyright (C) 2013 embedded brains GmbH
     5 *
     6 * Copyright (C) 2019 DornerWorks
     7 *
     8 * Written by Jeff Kubascik <jeff.kubascik@dornerworks.com>
     9 *        and Josh Whitehead <josh.whitehead@dornerworks.com>
    510 *
    611 * Redistribution and use in source and binary forms, with or without
     
    3439
    3540BSP_START_DATA_SECTION static const arm_cp15_start_section_config
    36 zynq_mmu_config_table[] = {
     41zynqmp_mmu_config_table[] = {
    3742  ARMV7_CP15_START_DEFAULT_SECTIONS,
    3843#if defined(RTEMS_SMP)
     
    4449#endif
    4550  {
    46     .begin = 0xe0000000U,
    47     .end = 0xe0200000U,
     51    .begin = 0xf9000000U,
     52    .end = 0xf9100000U,
    4853    .flags = ARMV7_MMU_DEVICE
    4954  }, {
    50     .begin = 0xf8000000U,
    51     .end = 0xf9000000U,
     55    .begin = 0xfd000000U,
     56    .end = 0xffc00000U,
    5257    .flags = ARMV7_MMU_DEVICE
    5358  }
     
    5762 * Make weak and let the user override.
    5863 */
    59 BSP_START_TEXT_SECTION void zynq_setup_mmu_and_cache(void) __attribute__ ((weak));
     64BSP_START_TEXT_SECTION void zynqmp_setup_mmu_and_cache(void) __attribute__ ((weak));
    6065
    61 BSP_START_TEXT_SECTION void zynq_setup_mmu_and_cache(void)
     66BSP_START_TEXT_SECTION void zynqmp_setup_mmu_and_cache(void)
    6267{
    6368  uint32_t ctrl = arm_cp15_start_setup_mmu_and_cache(
    64     ARM_CP15_CTRL_A,
     69    ARM_CP15_CTRL_TRE | ARM_CP15_CTRL_A,
    6570    ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z
    6671  );
     
    7075    (uint32_t *) bsp_translation_table_base,
    7176    ARM_MMU_DEFAULT_CLIENT_DOMAIN,
    72     &zynq_mmu_config_table[0],
    73     RTEMS_ARRAY_SIZE(zynq_mmu_config_table)
     77    &zynqmp_mmu_config_table[0],
     78    RTEMS_ARRAY_SIZE(zynqmp_mmu_config_table)
    7479  );
    7580}
  • bsps/arm/xilinx-zynqmp/start/linkcmds.in

    r677d5167 r77f9a1b  
    11MEMORY {
    2    RAM_INT_0 : ORIGIN = @ZYNQ_RAM_INT_0_ORIGIN@, LENGTH = @ZYNQ_RAM_INT_0_LENGTH@
    3    RAM_INT_1 : ORIGIN = @ZYNQ_RAM_INT_1_ORIGIN@, LENGTH = @ZYNQ_RAM_INT_1_LENGTH@
    4    RAM_MMU   : ORIGIN = @ZYNQ_RAM_MMU@, LENGTH = @ZYNQ_RAM_MMU_LENGTH@
    5    RAM       : ORIGIN = @ZYNQ_RAM_ORIGIN_AVAILABLE@, LENGTH = @ZYNQ_RAM_LENGTH_AVAILABLE@ - @ZYNQ_RAM_NOCACHE_LENGTH@
    6    NOCACHE   : ORIGIN = @ZYNQ_RAM_ORIGIN_AVAILABLE@ + @ZYNQ_RAM_LENGTH_AVAILABLE@ - @ZYNQ_RAM_NOCACHE_LENGTH@, LENGTH = @ZYNQ_RAM_NOCACHE_LENGTH@
     2   RAM_INT_0 : ORIGIN = @ZYNQMP_RAM_INT_0_ORIGIN@, LENGTH = @ZYNQMP_RAM_INT_0_LENGTH@
     3   RAM_INT_1 : ORIGIN = @ZYNQMP_RAM_INT_1_ORIGIN@, LENGTH = @ZYNQMP_RAM_INT_1_LENGTH@
     4   RAM_MMU   : ORIGIN = @ZYNQMP_RAM_MMU@, LENGTH = @ZYNQMP_RAM_MMU_LENGTH@
     5   RAM       : ORIGIN = @ZYNQMP_RAM_ORIGIN_AVAILABLE@, LENGTH = @ZYNQMP_RAM_LENGTH_AVAILABLE@ - @ZYNQMP_RAM_NOCACHE_LENGTH@
     6   NOCACHE   : ORIGIN = @ZYNQMP_RAM_ORIGIN_AVAILABLE@ + @ZYNQMP_RAM_LENGTH_AVAILABLE@ - @ZYNQMP_RAM_NOCACHE_LENGTH@, LENGTH = @ZYNQMP_RAM_NOCACHE_LENGTH@
    77}
    88
  • c/src/lib/libbsp/arm/acinclude.m4

    r677d5167 r77f9a1b  
    4343  xilinx-zynq )
    4444    AC_CONFIG_SUBDIRS([xilinx-zynq]);;
     45  xilinx-zynqmp )
     46    AC_CONFIG_SUBDIRS([xilinx-zynqmp]);;
    4547  *)
    4648    AC_MSG_ERROR([Invalid BSP]);;
  • c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am

    r677d5167 r77f9a1b  
    33# @file
    44#
    5 # @brief Makefile of LibBSP for the Xilinx Zynq platform.
     5# @brief Makefile of LibBSP for the Xilinx Zynq UltraScale+ MPSoC platform.
    66#
    77
     
    1111include $(top_srcdir)/../../bsp.am
    1212
    13 dist_project_lib_DATA = ../../../../../../bsps/arm/xilinx-zynq/start/bsp_specs
     13dist_project_lib_DATA = ../../../../../../bsps/arm/xilinx-zynqmp/start/bsp_specs
    1414
    1515###############################################################################
     
    4747
    4848# Startup
    49 librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/start/bspreset.c
    50 librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/start/bspstart.c
     49librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynqmp/start/bspreset.c
     50librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynqmp/start/bspstart.c
    5151if HAS_SMP
    5252librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/start/arm-a9mpcore-smp.c
    53 librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/start/bspsmp.c
     53librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynqmp/start/bspsmp.c
    5454endif
    5555
     
    6060# Console
    6161librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/console-termios.c
    62 librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/console/console-config.c
    63 librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/console/debug-console.c
     62librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynqmp/console/console-config.c
    6463librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/serial/zynq-uart.c
    6564
    6665# Clock
    67 librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/clock/clock-a9mpcore.c
    68 
    69 # I2C
    70 librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/i2c/cadence-i2c.c
     66librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/clock/clock-generic-timer.c
    7167
    7268# Cache
    73 librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-l2c-310.c
     69librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c
    7470
    7571# Start hooks
    76 librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/start/bspstarthooks.c
    77 librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/start/bspstartmmu.c
     72librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynqmp/start/bspstarthooks.c
     73librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynqmp/start/bspstartmmu.c
    7874
    7975###############################################################################
     
    8480include $(srcdir)/../../../../../../bsps/shared/irq-sources.am
    8581include $(srcdir)/../../../../../../bsps/shared/shared-sources.am
    86 include $(srcdir)/../../../../../../bsps/arm/xilinx-zynq/headers.am
     82include $(srcdir)/../../../../../../bsps/arm/xilinx-zynqmp/headers.am
  • c/src/lib/libbsp/arm/xilinx-zynqmp/configure.ac

    r677d5167 r77f9a1b  
    33# @file
    44#
    5 # @brief Configure script of LibBSP for the Xilinx Zynq platform.
     5# @brief Configure script of LibBSP for the Xilinx Zynq UltraScale+ MPSoC platform.
    66#
    77
    88AC_PREREQ([2.69])
    9 AC_INIT([rtems-c-src-lib-libbsp-arm-xilinx-zynq-a9],[_RTEMS_VERSION],[https://devel.rtems.org/newticket])
     9AC_INIT([rtems-c-src-lib-libbsp-arm-xilinx-zynqmp-a53],[_RTEMS_VERSION],[https://devel.rtems.org/newticket])
    1010RTEMS_TOP(../../../../../..)
    1111RTEMS_SOURCE_TOP
     
    2929RTEMS_BSPOPTS_HELP([BSP_INSTRUCTION_CACHE_ENABLED],[enable instruction cache])
    3030
    31 RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[xilinx_zynq_zc702*],[333333333U])
    32 RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[xilinx_zynq_zedboard*],[666666667U])
    33 RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[*],[100000000U])
    34 RTEMS_BSPOPTS_HELP([BSP_ARM_A9MPCORE_PERIPHCLK],[ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz])
     31RTEMS_BSPOPTS_SET([ARM_GENERIC_TIMER_USE_VIRTUAL],[*],[])
     32RTEMS_BSPOPTS_HELP([ARM_GENERIC_TIMER_USE_VIRTUAL],[Use virtual ARM generic timer])
    3533
    36 RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[xilinx_zynq_zc702*],[50000000UL])
    37 RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[xilinx_zynq_zedboard*],[50000000UL])
    38 RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[*],[50000000UL])
     34RTEMS_BSPOPTS_SET([ARM_GENERIC_TIMER_FREQ],[*],[])
     35RTEMS_BSPOPTS_HELP([ARM_GENERIC_TIMER_FREQ],[ARM generic timer frequency in Hz])
     36
     37RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[xilinx_zynqmp_ultra96*],[100000000UL])
     38RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[*],[100000000UL])
    3939RTEMS_BSPOPTS_HELP([ZYNQ_CLOCK_UART],[Zynq UART clock frequency in Hz])
    4040
    41 RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_CPU_1X],[xilinx_zynq_zc702*],[111111111U])
    42 RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_CPU_1X],[xilinx_zynq_zedboard*],[111111111U])
    43 RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_CPU_1X],[*],[111111111U])
    44 RTEMS_BSPOPTS_HELP([ZYNQ_CLOCK_CPU_1X],[Zynq cpu_1x clock frequency in Hz])
    45 
    4641USE_FAST_IDLE=0
    47 AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_a9_qemu], [USE_FAST_IDLE=1])
     42AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynqmp_a53_qemu], [USE_FAST_IDLE=1])
    4843
    4944RTEMS_BSPOPTS_SET([CLOCK_DRIVER_USE_FAST_IDLE],[*qemu],[${USE_FAST_IDLE}])
     
    6257# Zynq Memory map can be controlled from the configure command line. Use ...
    6358#
    64 #   ..../configure --target=arm-rtems4.11 ... BSP_ZYNQ_RAM_LENGTH=256M
     59#   ..../configure --target=arm-rtems4.11 ... BSP_ZYNQMP_RAM_LENGTH=256M
    6560#
    66 RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_a9_qemu],[256M])
    67 RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zc702],[1024M])
    68 RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zc706],[1024M])
    69 RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zedboard],[512M])
    70 RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[*],[256M])
    71 RTEMS_BSPOPTS_HELP([BSP_ZYNQ_RAM_LENGTH],[override a BSP's default RAM length])
     61RTEMS_BSPOPTS_SET([BSP_ZYNQMP_RAM_LENGTH],[xilinx_zynqmp_ultra96],[2048M])
     62RTEMS_BSPOPTS_SET([BSP_ZYNQMP_RAM_LENGTH],[*],[256M])
     63RTEMS_BSPOPTS_HELP([BSP_ZYNQMP_RAM_LENGTH],[override a BSP's default RAM length])
    7264
    73 RTEMS_BSPOPTS_SET([BSP_ZYNQ_NOCACHE_LENGTH],[*],[1M])
    74 RTEMS_BSPOPTS_HELP([BSP_ZYNQ_NOCACHE_LENGTH],[length of nocache RAM region])
     65RTEMS_BSPOPTS_SET([BSP_ZYNQMP_NOCACHE_LENGTH],[*],[1M])
     66RTEMS_BSPOPTS_HELP([BSP_ZYNQMP_NOCACHE_LENGTH],[length of nocache RAM region])
    7567
    76 AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_a9_qemu],
    77       [ZYNQ_RAM_ORIGIN="0x00000000"
    78        ZYNQ_RAM_MMU="0x0fffc000"
    79        ZYNQ_RAM_MMU_LENGTH="16k"
    80        ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN}"
    81        ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 16k"
    82        ZYNQ_RAM_INT_0_ORIGIN="0x00000000"
    83        ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
    84        ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000"
    85        ZYNQ_RAM_INT_1_LENGTH="64k - 512"])
     68AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynqmp_a53_qemu],
     69      [ZYNQMP_RAM_ORIGIN="0x00000000"
     70       ZYNQMP_RAM_MMU="0x0fffc000"
     71       ZYNQMP_RAM_MMU_LENGTH="16k"
     72       ZYNQMP_RAM_ORIGIN_AVAILABLE="${ZYNQMP_RAM_ORIGIN}"
     73       ZYNQMP_RAM_LENGTH_AVAILABLE="${BSP_ZYNQMP_RAM_LENGTH} - 16k"
     74       ZYNQMP_RAM_INT_0_ORIGIN="0x00000000"
     75       ZYNQMP_RAM_INT_0_LENGTH="64k + 64k + 64k"
     76       ZYNQMP_RAM_INT_1_ORIGIN="0xFFFF0000"
     77       ZYNQMP_RAM_INT_1_LENGTH="64k - 512"])
    8678
    87 AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zc702],
    88       [ZYNQ_RAM_ORIGIN="0x00100000"
    89        ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}"
    90        ZYNQ_RAM_MMU_LENGTH="16k"
    91        ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000"
    92        ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 1M - 16k"
    93        ZYNQ_RAM_INT_0_ORIGIN="0x00000000"
    94        ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
    95        ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000"
    96        ZYNQ_RAM_INT_1_LENGTH="64k - 512"])
     79AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynqmp_ultra96],
     80      [ZYNQMP_RAM_ORIGIN="0x00100000"
     81       ZYNQMP_RAM_MMU="${ZYNQMP_RAM_ORIGIN}"
     82       ZYNQMP_RAM_MMU_LENGTH="16k"
     83       ZYNQMP_RAM_ORIGIN_AVAILABLE="${ZYNQMP_RAM_ORIGIN} + 0x00004000"
     84       ZYNQMP_RAM_LENGTH_AVAILABLE="${BSP_ZYNQMP_RAM_LENGTH} - 1M - 16k"
     85       ZYNQMP_RAM_INT_0_ORIGIN="0x00000000"
     86       ZYNQMP_RAM_INT_0_LENGTH="64k + 64k + 64k"
     87       ZYNQMP_RAM_INT_1_ORIGIN="0xFFFF0000"
     88       ZYNQMP_RAM_INT_1_LENGTH="64k - 512"])
    9789
    98 AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zc706],
    99       [ZYNQ_RAM_ORIGIN="0x00400000"
    100        ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}"
    101        ZYNQ_RAM_MMU_LENGTH="16k"
    102        ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000"
    103        ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 4M - 16k"
    104        ZYNQ_RAM_INT_0_ORIGIN="0x00000000"
    105        ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
    106        ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000"
    107        ZYNQ_RAM_INT_1_LENGTH="64k - 512"])
    108 
    109 AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zedboard],
    110       [ZYNQ_RAM_ORIGIN="0x00100000"
    111        ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}"
    112        ZYNQ_RAM_MMU_LENGTH="16k"
    113        ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000"
    114        ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 1M - 16k"
    115        ZYNQ_RAM_INT_0_ORIGIN="0x00000000"
    116        ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
    117        ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000"
    118        ZYNQ_RAM_INT_1_LENGTH="64k - 512"])
    119 
    120 AC_DEFUN([ZYNQ_LINKCMD],[
     90AC_DEFUN([ZYNQMP_LINKCMD],[
    12191AC_ARG_VAR([$1],[$2; default $3])dnl
    12292[$1]=[$]{[$1]:-[$3]}
    12393])
    12494
    125 ZYNQ_LINKCMD([ZYNQ_RAM_ORIGIN],[normal RAM region origin],[${ZYNQ_RAM_ORIGIN}])
    126 ZYNQ_LINKCMD([ZYNQ_RAM_LENGTH],[normal RAM region length],[${BSP_ZYNQ_RAM_LENGTH}])
    127 ZYNQ_LINKCMD([ZYNQ_RAM_MMU],[MMU region origin],[${ZYNQ_RAM_MMU}])
    128 ZYNQ_LINKCMD([ZYNQ_RAM_MMU_LENGTH],[MMU region length],[${ZYNQ_RAM_MMU_LENGTH}])
    129 ZYNQ_LINKCMD([ZYNQ_RAM_ORIGIN_AVAILABLE],[origin of available RAM],[${ZYNQ_RAM_ORIGIN_AVAILABLE}])
    130 ZYNQ_LINKCMD([ZYNQ_RAM_LENGTH_AVAILABLE],[length of available RAM],[${ZYNQ_RAM_LENGTH_AVAILABLE}])
    131 ZYNQ_LINKCMD([ZYNQ_RAM_NOCACHE_LENGTH],[length of nocache RAM region],[${BSP_ZYNQ_NOCACHE_LENGTH}])
    132 ZYNQ_LINKCMD([ZYNQ_RAM_INT_0_ORIGIN],[internal 0 RAM region origin],[${ZYNQ_RAM_INT_0_ORIGIN}])
    133 ZYNQ_LINKCMD([ZYNQ_RAM_INT_0_LENGTH],[internal 0 RAM region length],[${ZYNQ_RAM_INT_0_LENGTH}])
    134 ZYNQ_LINKCMD([ZYNQ_RAM_INT_1_ORIGIN],[internal 1 RAM region origin],[${ZYNQ_RAM_INT_1_ORIGIN}])
    135 ZYNQ_LINKCMD([ZYNQ_RAM_INT_1_LENGTH],[internal 1 RAM region length],[${ZYNQ_RAM_INT_1_LENGTH}])
     95ZYNQMP_LINKCMD([ZYNQMP_RAM_ORIGIN],[normal RAM region origin],[${ZYNQMP_RAM_ORIGIN}])
     96ZYNQMP_LINKCMD([ZYNQMP_RAM_LENGTH],[normal RAM region length],[${BSP_ZYNQMP_RAM_LENGTH}])
     97ZYNQMP_LINKCMD([ZYNQMP_RAM_MMU],[MMU region origin],[${ZYNQMP_RAM_MMU}])
     98ZYNQMP_LINKCMD([ZYNQMP_RAM_MMU_LENGTH],[MMU region length],[${ZYNQMP_RAM_MMU_LENGTH}])
     99ZYNQMP_LINKCMD([ZYNQMP_RAM_ORIGIN_AVAILABLE],[origin of available RAM],[${ZYNQMP_RAM_ORIGIN_AVAILABLE}])
     100ZYNQMP_LINKCMD([ZYNQMP_RAM_LENGTH_AVAILABLE],[length of available RAM],[${ZYNQMP_RAM_LENGTH_AVAILABLE}])
     101ZYNQMP_LINKCMD([ZYNQMP_RAM_NOCACHE_LENGTH],[length of nocache RAM region],[${BSP_ZYNQMP_NOCACHE_LENGTH}])
     102ZYNQMP_LINKCMD([ZYNQMP_RAM_INT_0_ORIGIN],[internal 0 RAM region origin],[${ZYNQMP_RAM_INT_0_ORIGIN}])
     103ZYNQMP_LINKCMD([ZYNQMP_RAM_INT_0_LENGTH],[internal 0 RAM region length],[${ZYNQMP_RAM_INT_0_LENGTH}])
     104ZYNQMP_LINKCMD([ZYNQMP_RAM_INT_1_ORIGIN],[internal 1 RAM region origin],[${ZYNQMP_RAM_INT_1_ORIGIN}])
     105ZYNQMP_LINKCMD([ZYNQMP_RAM_INT_1_LENGTH],[internal 1 RAM region length],[${ZYNQMP_RAM_INT_1_LENGTH}])
    136106
    137107RTEMS_BSP_CLEANUP_OPTIONS
     
    139109AC_CONFIG_FILES([
    140110Makefile
    141 linkcmds:../../../../../../bsps/arm/xilinx-zynq/start/linkcmds.in])
     111linkcmds:../../../../../../bsps/arm/xilinx-zynqmp/start/linkcmds.in])
    142112AC_OUTPUT
Note: See TracChangeset for help on using the changeset viewer.