Changeset 76918e1 in rtems for bsps


Ignore:
Timestamp:
Feb 28, 2019, 9:40:10 AM (10 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
a3db5001
Parents:
8e8e269
git-author:
Sebastian Huber <sebastian.huber@…> (02/28/19 09:40:10)
git-committer:
Sebastian Huber <sebastian.huber@…> (02/28/19 10:52:30)
Message:

bsps/arm: Add BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0

The following variants

  • GICv1 with Security Extensions,
  • GICv2 without Security Extensions, or
  • within Secure processor mode

have the ability to assign group 0 or 1 to individual interrupts. Group
0 interrupts can be configured to raise an FIQ exception. This enables
the use of NMIs with respect to RTEMS.

BSPs can enable this feature with the BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
define. Use arm_gic_irq_set_group() to change the group of an
interrupt (default group is 1, if BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 is
defined).

Location:
bsps/arm
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • bsps/arm/include/bsp/arm-gic-irq.h

    r8e8e269 r76918e1  
    9999    dist->icdsgir = GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(filter)
    100100      | GIC_DIST_ICDSGIR_CPU_TARGET_LIST(targets)
     101#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
     102      | GIC_DIST_ICDSGIR_NSATT
     103#endif
    101104      | GIC_DIST_ICDSGIR_SGIINTID(vector);
    102105  } else {
  • bsps/arm/shared/irq/irq-gic.c

    r8e8e269 r76918e1  
    2727#define PRIORITY_DEFAULT 127
    2828
     29/*
     30 * The following variants
     31 *
     32 *  - GICv1 with Security Extensions,
     33 *  - GICv2 without Security Extensions, or
     34 *  - within Secure processor mode
     35 *
     36 * have the ability to assign group 0 or 1 to individual interrupts.  Group
     37 * 0 interrupts can be configured to raise an FIQ exception.  This enables
     38 * the use of NMIs with respect to RTEMS.
     39 *
     40 * BSPs can enable this feature with the BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
     41 * define.  Use arm_gic_irq_set_group() to change the group of an
     42 * interrupt (default group is 1, if BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 is
     43 * defined).
     44 */
     45#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
     46#define DIST_ICDDCR (GIC_DIST_ICDDCR_ENABLE_GRP_1 | GIC_DIST_ICDDCR_ENABLE)
     47#define CPUIF_ICCICR \
     48  (GIC_CPUIF_ICCICR_CBPR | GIC_CPUIF_ICCICR_FIQ_EN \
     49    | GIC_CPUIF_ICCICR_ACK_CTL | GIC_CPUIF_ICCICR_ENABLE_GRP_1 \
     50    | GIC_CPUIF_ICCICR_ENABLE)
     51#else
     52#define DIST_ICDDCR GIC_DIST_ICDDCR_ENABLE
     53#define CPUIF_ICCICR GIC_CPUIF_ICCICR_ENABLE
     54#endif
     55
    2956void bsp_interrupt_dispatch(void)
    3057{
     
    73100}
    74101
     102static void enable_fiq(void)
     103{
     104#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
     105  rtems_interrupt_level level;
     106
     107  rtems_interrupt_local_disable(level);
     108  level &= ~ARM_PSR_F;
     109  rtems_interrupt_local_enable(level);
     110#endif
     111}
     112
    75113rtems_status_code bsp_interrupt_facility_initialize(void)
    76114{
     
    86124
    87125  for (id = 0; id < id_count; id += 32) {
     126#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
     127    dist->icdigr[id / 32] = 0xffffffff;
     128#endif
    88129    dist->icdicer[id / 32] = 0xffffffff;
    89130  }
     
    99140  cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff);
    100141  cpuif->iccbpr = GIC_CPUIF_ICCBPR_BINARY_POINT(0x0);
    101   cpuif->iccicr = GIC_CPUIF_ICCICR_ENABLE;
    102 
    103   dist->icddcr = GIC_DIST_ICDDCR_ENABLE;
    104 
     142  cpuif->iccicr = CPUIF_ICCICR;
     143
     144  dist->icddcr = GIC_DIST_ICDDCR_ENABLE_GRP_1 | GIC_DIST_ICDDCR_ENABLE;
     145
     146  enable_fiq();
    105147  return RTEMS_SUCCESSFUL;
    106148}
     
    116158  }
    117159
     160#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
     161  dist->icdigr[0] = 0xffffffff;
     162#endif
     163
    118164  cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff);
    119165  cpuif->iccbpr = GIC_CPUIF_ICCBPR_BINARY_POINT(0x0);
    120   cpuif->iccicr = GIC_CPUIF_ICCICR_ENABLE;
     166  cpuif->iccicr = CPUIF_ICCICR;
     167
     168  enable_fiq();
    121169}
    122170#endif
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