Changeset 767cdd8 in rtems


Ignore:
Timestamp:
Jul 11, 2008, 10:04:40 AM (11 years ago)
Author:
Thomas Doerfler <Thomas.Doerfler@…>
Branches:
4.10, 4.11, 4.9, master
Children:
e0b8176
Parents:
80a0ae8
Message:

adapted for modified exception code

Location:
cpukit/score/cpu/powerpc
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/powerpc/ChangeLog

    r80a0ae8 r767cdd8  
     12008-07-10      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * rtems/asm.h: Added defines for save and restore registers and
     4        special purpose registers 4 to 7.
     5
     6        * rtems/new-exceptions/cpu.h: Changed define PPC_BSP_HAS_FIXED_PR288 to
     7        a value that results in a compile time error on usage since SPRG0 is
     8        now used for the interrupt disable mask.
     9
     10        * rtems/powerpc/registers.h: Bugfix: Swapped values of TBWU and TBWL.
     11
     12        Added defines SPRG4..7 and USPRG0.
     13
     14        Changed _CPU_ISR_{Disable, Enable, Flush} to use static inline
     15        functions.  The interrupt disable mask is now stored in SPRG0.  Which
     16        was previously denoted to indicate a PR288 bugfix.  You may now
     17        initialize the interrupt disable mask via
     18        ppc_interrupt_set_disable_mask() and
     19        PPC_INTERRUPT_DISABLE_MASK_DEFAULT.  The default value will be set in
     20        bootcard.c.
     21
    1222008-02-20      Ralf Corsépius <ralf.corsepius@rtems.org>
    223
  • cpukit/score/cpu/powerpc/rtems/asm.h

    r80a0ae8 r767cdd8  
    158158#define srr0    0x01a
    159159#define srr1    0x01b
    160 #if defined(ppc403) || defined(ppc405)
    161 #define srr2    0x3de   /* IBM 400 series only */
    162 #define srr3    0x3df   /* IBM 400 series only */
    163 #endif /* ppc403 or ppc405 */
     160#define srr2    0x3de /* IBM 400 series only */
     161#define srr3    0x3df /* IBM 400 series only */
     162#define csrr0   58 /* Book E */
     163#define csrr1   59 /* Book E */
     164#define mcsrr0  570 /* e500 */
     165#define mcsrr1  571 /* e500 */
     166#define dsrr0   574 /* e200 */
     167#define dsrr1   575 /* e200 */
    164168
    165169#define sprg0   0x110
     
    167171#define sprg2   0x112
    168172#define sprg3   0x113
     173#define sprg4   276
     174#define sprg5   277
     175#define sprg6   278
     176#define sprg7   279
     177
     178#define usprg0  256
    169179
    170180#define dar     0x013   /* Data Address Register */
  • cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h

    r80a0ae8 r767cdd8  
    312312
    313313/*
    314  *  Until all new-exception processing BSPs have fixed
    315  *  PR288, we let the good BSPs pass
    316  *
    317  *  PPC_BSP_HAS_FIXED_PR288
    318  *
    319  *  in SPRG0 and let _CPU_Initialize assert this.
    320  */
    321 
    322 #define PPC_BSP_HAS_FIXED_PR288 0x600dbabe
     314 * SPRG0 was previously used to make sure that the BSP fixed the PR288 bug.
     315 * Now SPRG0 is devoted to the interrupt disable mask.
     316 */
     317
     318#define PPC_BSP_HAS_FIXED_PR288 ppc_this_is_now_the_interrupt_disable_mask
    323319
    324320#endif /* ASM */
  • cpukit/score/cpu/powerpc/rtems/powerpc/registers.h

    r80a0ae8 r767cdd8  
    1818#ifndef _RTEMS_POWERPC_REGISTERS_H
    1919#define _RTEMS_POWERPC_REGISTERS_H
    20 
    21 #ifdef __cplusplus
    22 extern "C" {
    23 #endif
    2420
    2521/* Bit encodings for Machine State Register (MSR) */
     
    3834#define MSR_DE          (1<<9)          /* BookE debug exception */
    3935#define MSR_FE1         (1<<8)          /* Floating Exception mode 1 */
     36#define MSR_E300_CE     (1<<7)          /* e300 critical interrupt */
    4037#define MSR_IP          (1<<6)          /* Exception prefix 0x000/0xFFF */
    4138#define MSR_IR          (1<<5)          /* Instruction MMU enable */
     
    121118#define TBRU    269     /* Time base Upper/Lower (Reading) */
    122119#define TBRL    268
    123 #define TBWU    284     /* Time base Upper/Lower (Writing) */
    124 #define TBWL    285
     120#define TBWU    285     /* Time base Upper/Lower (Writing) */
     121#define TBWL    284
    125122#define XER     1
    126123#define LR      8
     
    185182#define SPR3    275
    186183#define SPRG3   275
     184#define SPRG4   276
     185#define SPRG5   277
     186#define SPRG6   278
     187#define SPRG7   279
     188#define USPRG0  256
    187189#define DSISR   18
    188190#define SRR0    26      /* Saved Registers (exception) */
     
    308310#define BOOKE_TCR_FPEXT(x)      (((x)&0xf)<<13)
    309311
     312/**
     313 * @brief Default value for the interrupt disable mask.
     314 *
     315 * The interrupt disable mask is stored in the SPRG0 (= special purpose
     316 * register 272).
     317 */
     318#define PPC_INTERRUPT_DISABLE_MASK_DEFAULT MSR_EE
     319
     320#ifndef ASM
     321
     322#include <stdint.h>
     323
     324#ifdef __cplusplus
     325extern "C" {
     326#endif /* __cplusplus */
     327
    310328#define _CPU_MSR_GET( _msr_value ) \
    311329  do { \
     
    317335{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
    318336
     337static inline void ppc_interrupt_set_disable_mask( uint32_t mask)
     338{
     339  asm volatile (
     340    "mtspr 272, %0"
     341    :
     342    : "r" (mask)
     343  );
     344}
     345
     346static inline uint32_t ppc_interrupt_disable()
     347{
     348  uint32_t level;
     349  uint32_t mask;
     350
     351  asm volatile (
     352    "mfmsr %0;"
     353    "mfspr %1, 272;"
     354    "andc %1, %0, %1;"
     355    "mtmsr %1"
     356    : "=r" (level), "=r" (mask)
     357  );
     358
     359  return level;
     360}
     361
     362static inline void ppc_interrupt_enable( uint32_t level)
     363{
     364  asm volatile (
     365    "mtmsr %0"
     366    :
     367    : "r" (level)
     368  );
     369}
     370
     371static inline void ppc_interrupt_flash( uint32_t level)
     372{
     373  uint32_t current_level;
     374
     375  asm volatile (
     376    "mfmsr %0;"
     377    "mtmsr %1;"
     378    "mtmsr %0"
     379    : "=&r" (current_level)
     380    : "r" (level)
     381  );
     382}
     383
    319384#define _CPU_ISR_Disable( _isr_cookie ) \
    320   { register unsigned int _disable_mask = MSR_EE; \
    321     _isr_cookie = 0; \
    322     asm volatile ( \
    323         "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
    324         "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
    325         "0" ((_isr_cookie)), "1" ((_disable_mask)) \
    326         ); \
    327   }
    328 
     385  do { \
     386    _isr_cookie = ppc_interrupt_disable(); \
     387  } while (0)
    329388
    330389/*
     
    335394
    336395#define _CPU_ISR_Enable( _isr_cookie )  \
    337   { \
    338      asm volatile ( "mtmsr %0" : \
    339                    "=r" ((_isr_cookie)) : \
    340                    "0" ((_isr_cookie))); \
    341   }
     396  ppc_interrupt_enable( _isr_cookie)
    342397
    343398/*
     
    353408
    354409#define _CPU_ISR_Flash( _isr_cookie ) \
    355   { register unsigned int _disable_mask = MSR_EE; \
    356     asm volatile ( \
    357       "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
    358       "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
    359       "0" ((_isr_cookie)), "1" ((_disable_mask)) \
    360     ); \
    361   }
    362 
     410  ppc_interrupt_flash( _isr_cookie)
    363411
    364412/* end of ISR handler macros */
     
    366414#ifdef __cplusplus
    367415}
    368 #endif
     416#endif /* __cplusplus */
     417
     418#endif /* ASM */
    369419
    370420#endif /* _RTEMS_POWERPC_REGISTERS_H */
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