Changeset 7633f5b in rtems


Ignore:
Timestamp:
Mar 12, 2018, 5:59:15 AM (14 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
71c5552f
Parents:
8b5778e
git-author:
Sebastian Huber <sebastian.huber@…> (03/12/18 05:59:15)
git-committer:
Sebastian Huber <sebastian.huber@…> (03/13/18 07:05:40)
Message:

sparc64: Move libcpu content to cpukit

This patch is a part of the BSP source reorganization.

Update #3285.

Files:
3 deleted
6 edited
3 moved

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/sparc64/niagara/Makefile.am

    r8b5778e r7633f5b  
    5353libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
    5454
    55 libbsp_a_LIBADD = \
    56       ../../../libcpu/@RTEMS_CPU@/shared/shared-score.rel \
    57       ../../../libcpu/@RTEMS_CPU@/shared/sparc64-syscall.rel
    58 
    5955include $(top_srcdir)/../../../../automake/local.am
    6056include $(srcdir)/../../../../../../bsps/sparc64/niagara/headers.am
  • c/src/lib/libbsp/sparc64/niagara/make/custom/niagara.cfg

    r8b5778e r7633f5b  
    55
    66RTEMS_CPU=sparc64
    7 RTEMS_CPU_MODEL=sun4v
    8 
    9 # This is the actual bsp directory used during the build process.
    10 RTEMS_BSP_FAMILY=niagara
    117
    128#  This contains the compiler options necessary to select the CPU model
  • c/src/lib/libbsp/sparc64/usiii/Makefile.am

    r8b5778e r7633f5b  
    6666libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
    6767
    68 libbsp_a_LIBADD = \
    69       ../../../libcpu/@RTEMS_CPU@/shared/shared-score.rel \
    70       ../../../libcpu/@RTEMS_CPU@/shared/sparc64-syscall.rel
    71 
    7268include $(top_srcdir)/../../../../automake/local.am
    7369include $(srcdir)/../../../../../../bsps/sparc64/usiii/headers.am
  • c/src/lib/libbsp/sparc64/usiii/make/custom/usiii.cfg

    r8b5778e r7633f5b  
    55
    66RTEMS_CPU=sparc64
    7 RTEMS_CPU_MODEL=sun4u
    8 
    9 # This is the actual bsp directory used during the build process.
    10 RTEMS_BSP_FAMILY=usiii
    117
    128#  This contains the compiler options necessary to select the CPU model
  • cpukit/score/cpu/sparc64/Makefile.am

    r8b5778e r7633f5b  
    11include $(top_srcdir)/automake/compile.am
    22
    3 #include_rtems_sparc64dir = $(includedir)/rtems/sparc64
    4 #include_rtems_sparc64_HEADERS =
    5 
    63noinst_LIBRARIES = libscorecpu.a
    7 libscorecpu_a_SOURCES = context.S cpu.c
     4libscorecpu_a_SOURCES =
     5libscorecpu_a_SOURCES += context.S
     6libscorecpu_a_SOURCES += cpu.c
     7libscorecpu_a_SOURCES += interrupt.S
    88libscorecpu_a_SOURCES += ../no_cpu/cpucounterread.c
    99libscorecpu_a_SOURCES += sparc64-exception-frame-print.c
    10 libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)
     10libscorecpu_a_SOURCES += sparc64-syscall.S
    1111
    1212include $(top_srcdir)/automake/local.am
  • cpukit/score/cpu/sparc64/cpu.c

    r8b5778e r7633f5b  
    111111  }
    112112}
     113
     114/*
     115 *  This initializes the set of opcodes placed in each trap
     116 *  table entry.  The routine which installs a handler is responsible
     117 *  for filling in the fields for the _handler address and the _vector
     118 *  trap type.
     119 *
     120 *  The constants following this structure are masks for the fields which
     121 *  must be filled in when the handler is installed.
     122 */
     123
     124/*  64-bit registers complicate this. Also, in sparc v9,
     125 *      each trap level gets its own set of global registers, but
     126 *      does not get its own dedicated register window. so we avoid
     127 *      using the local registers in the trap handler.
     128 */
     129const CPU_Trap_table_entry _CPU_Trap_slot_template = {
     130  0x89508000,   /* rdpr   %tstate, %g4       */
     131  0x05000000,   /* sethi %hh(_handler), %g2  */
     132  0x8410a000,   /* or     %g2, %hm(_handler), %g2 */
     133  0x8528b020,   /* sllx   %g2, 32, %g2 */
     134  0x07000000,   /* sethi  %hi(_handler), %g3 */
     135  0x8610c002,   /* or     %g3, %g2, %g3 */
     136  0x81c0e000, /* jmp   %g3 + %lo(_handler) */
     137  0x84102000  /* mov   _vector, %g2        */
     138};
     139
     140
     141/*
     142 *  _CPU_ISR_Get_level
     143 *
     144 *  Input Parameters: NONE
     145 *
     146 *  Output Parameters:
     147 *    returns the current interrupt level (PIL field of the PSR)
     148 */
     149uint32_t   _CPU_ISR_Get_level( void )
     150{
     151  uint32_t   level;
     152
     153  sparc64_get_interrupt_level( level );
     154
     155  return level;
     156}
     157
     158/*
     159 *  _CPU_ISR_install_raw_handler
     160 *
     161 *  This routine installs the specified handler as a "raw" non-executive
     162 *  supported trap handler (a.k.a. interrupt service routine).
     163 *
     164 *  Input Parameters:
     165 *    vector      - trap table entry number plus synchronous
     166 *                    vs. asynchronous information
     167 *    new_handler - address of the handler to be installed
     168 *    old_handler - pointer to an address of the handler previously installed
     169 *
     170 *  Output Parameters: NONE
     171 *    *new_handler - address of the handler previously installed
     172 *
     173 *  NOTE:
     174 *
     175 *  On the SPARC v9, there are really only 512 vectors.  However, the executive
     176 *  has no easy, fast, reliable way to determine which traps are synchronous
     177 *  and which are asynchronous.  By default, traps return to the
     178 *  instruction which caused the interrupt.  So if you install a software
     179 *  trap handler as an executive interrupt handler (which is desirable since
     180 *  RTEMS takes care of window and register issues), then the executive needs
     181 *  to know that the return address is to the trap rather than the instruction
     182 *  following the trap.
     183 *
     184 *  So vectors 0 through 511 are treated as regular asynchronous traps which
     185 *  provide the "correct" return address.  Vectors 512 through 1023 are assumed
     186 *  by the executive to be synchronous and to require that the return be to the
     187 *  trapping instruction.
     188 *
     189 *  If you use this mechanism to install a trap handler which must reexecute
     190 *  the instruction which caused the trap, then it should be installed as
     191 *  a synchronous trap.  This will avoid the executive changing the return
     192 *  address.
     193 */
     194void _CPU_ISR_install_raw_handler(
     195  uint32_t    vector,
     196  proc_ptr    new_handler,
     197  proc_ptr   *old_handler
     198)
     199{
     200  uint32_t               real_vector;
     201  CPU_Trap_table_entry  *tba;
     202  CPU_Trap_table_entry  *slot;
     203  uint64_t               u64_tba;
     204  uint64_t               u64_handler;
     205
     206  /*
     207   *  Get the "real" trap number for this vector ignoring the synchronous
     208   *  versus asynchronous indicator included with our vector numbers.
     209   */
     210
     211  real_vector = SPARC_REAL_TRAP_NUMBER( vector );
     212
     213  /*
     214   *  Get the current base address of the trap table and calculate a pointer
     215   *  to the slot we are interested in.
     216   */
     217
     218  sparc64_get_tba( u64_tba );
     219
     220/*  u32_tbr &= 0xfffff000; */
     221  u64_tba &= 0xffffffffffff8000;  /* keep only trap base address */
     222
     223  tba = (CPU_Trap_table_entry *) u64_tba;
     224
     225  /* use array indexing to fill in lower bits -- require
     226   * CPU_Trap_table_entry to be full-sized. */
     227  slot = &tba[ real_vector ];
     228
     229  /*
     230   *  Get the address of the old_handler from the trap table.
     231   *
     232   *  NOTE: The old_handler returned will be bogus if it does not follow
     233   *        the RTEMS model.
     234   */
     235
     236  /* shift amount to shift of hi bits (31:10) */
     237#define HI_BITS_SHIFT  10
     238
     239  /* shift amount of hm bits (41:32) */
     240#define HM_BITS_SHIFT  32
     241
     242  /* shift amount of hh bits (63:42) */
     243#define HH_BITS_SHIFT  42
     244
     245  /* We're only interested in bits 0-9 of the immediate field*/
     246#define IMM_MASK    0x000003FF
     247
     248  if ( slot->rdpr_tstate_g4 == _CPU_Trap_slot_template.rdpr_tstate_g4 ) {
     249    u64_handler =
     250      (((uint64_t)((slot->sethi_of_hh_handler_to_g2 << HI_BITS_SHIFT) |
     251      (slot->or_g2_hm_handler_to_g2 & IMM_MASK))) << HM_BITS_SHIFT) |
     252      ((slot->sethi_of_handler_to_g3 << HI_BITS_SHIFT) |
     253      (slot->jmp_to_low_of_handler_plus_g3 & IMM_MASK));
     254    *old_handler = (proc_ptr) u64_handler;
     255  } else
     256    *old_handler = 0;
     257
     258  /*
     259   *  Copy the template to the slot and then fix it.
     260   */
     261
     262  *slot = _CPU_Trap_slot_template;
     263
     264  u64_handler = (uint64_t) new_handler;
     265
     266  /* mask for extracting %hh */
     267#define HH_BITS_MASK   0xFFFFFC0000000000
     268
     269  /* mask for extracting %hm */
     270#define HM_BITS_MASK   0x000003FF00000000
     271
     272  /* mask for extracting %hi */
     273#define HI_BITS_MASK   0x00000000FFFFFC00
     274
     275  /* mask for extracting %lo */
     276#define LO_BITS_MASK   0x00000000000003FF
     277
     278
     279  slot->mov_vector_g2 |= vector;
     280  slot->sethi_of_hh_handler_to_g2 |=
     281    (u64_handler & HH_BITS_MASK) >> HH_BITS_SHIFT;
     282  slot->or_g2_hm_handler_to_g2 |=
     283    (u64_handler & HM_BITS_MASK) >> HM_BITS_SHIFT;
     284  slot->sethi_of_handler_to_g3 |=
     285    (u64_handler & HI_BITS_MASK) >> HI_BITS_SHIFT;
     286  slot->jmp_to_low_of_handler_plus_g3 |= (u64_handler & LO_BITS_MASK);
     287
     288  /* need to flush icache after this !!! */
     289
     290  /* need to flush icache in case old trap handler is in cache */
     291  rtems_cache_invalidate_entire_instruction();
     292
     293}
     294
     295/*
     296 *  _CPU_ISR_install_vector
     297 *
     298 *  This kernel routine installs the RTEMS handler for the
     299 *  specified vector.
     300 *
     301 *  Input parameters:
     302 *    vector       - interrupt vector number
     303 *    new_handler  - replacement ISR for this vector number
     304 *    old_handler  - pointer to former ISR for this vector number
     305 *
     306 *  Output parameters:
     307 *    *old_handler - former ISR for this vector number
     308 */
     309void _CPU_ISR_install_vector(
     310  uint64_t    vector,
     311  proc_ptr    new_handler,
     312  proc_ptr   *old_handler
     313)
     314{
     315   uint64_t   real_vector;
     316   proc_ptr   ignored;
     317
     318  /*
     319   *  Get the "real" trap number for this vector ignoring the synchronous
     320   *  versus asynchronous indicator included with our vector numbers.
     321   */
     322   real_vector = SPARC_REAL_TRAP_NUMBER( vector );
     323   /*
     324    *  Return the previous ISR handler.
     325    */
     326
     327   *old_handler = _ISR_Vector_table[ vector ];
     328
     329   /*
     330    *  Install the wrapper so this ISR can be invoked properly.
     331    */
     332
     333   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
     334
     335   /*
     336    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
     337    *  be used by the _ISR_Handler so the user gets control.
     338    */
     339
     340    _ISR_Vector_table[ real_vector ] = new_handler;
     341}
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