Changeset 74fb4e1f in rtems


Ignore:
Timestamp:
Feb 25, 2005, 5:18:49 AM (16 years ago)
Author:
Jay Monkman <jtm@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
c743b48
Parents:
7cde240
Message:

2005-02-24 Jay Monkman <jtm@…>

  • Makefile.am, configure.ac: New CPU.
  • shared/interrupts/installisrentries.c, shared/interrupts/isr_entries.S: Added CPU32 support.
  • au1x00/Makefile.am, au1x00/include/au1x00.h, au1x00/vectorisrs/maxvectors.c, au1x00/vectorisrs/vectorisrs.c: New CPU.
Location:
c/src/lib/libcpu/mips
Files:
4 added
5 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/mips/ChangeLog

    r7cde240 r74fb4e1f  
     12005-02-24      Jay Monkman <jtm@lopingdog.com>
     2
     3        * Makefile.am, configure.ac: New CPU.
     4        * shared/interrupts/installisrentries.c,
     5        shared/interrupts/isr_entries.S: Added CPU32 support.
     6        * au1x00/Makefile.am, au1x00/include/au1x00.h,
     7        au1x00/vectorisrs/maxvectors.c, au1x00/vectorisrs/vectorisrs.c: New CPU.
     8
    192005-01-07      Ralf Corsepius <ralf.corsepius@rtems.org>
    210
  • c/src/lib/libcpu/mips/Makefile.am

    r7cde240 r74fb4e1f  
    55ACLOCAL_AMFLAGS = -I ../../../aclocal
    66
    7 SUBDIRS = shared mongoosev tx39 r46xx
     7SUBDIRS = shared mongoosev tx39 r46xx au1x00
    88
    99include $(top_srcdir)/../../../automake/subdirs.am
  • c/src/lib/libcpu/mips/configure.ac

    r7cde240 r74fb4e1f  
    3131AM_CONDITIONAL(mongoosev, test "$RTEMS_CPU_MODEL" = "mongoosev")
    3232
     33AM_CONDITIONAL(au1x00, test "$RTEMS_CPU_MODEL" = "au1x00")
     34
    3335# Explicitly list all Makefiles here
    3436AC_CONFIG_FILES([Makefile
     37au1x00/Makefile
    3538mongoosev/Makefile
    3639shared/Makefile
  • c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c

    r7cde240 r74fb4e1f  
    1919  memcpy( (void *)E_VEC, exc_norm_code, 40 );   /* exception vevtor */
    2020
     21#elif __mips == 32
     22  void exc_tlb_code(void);
     23  void exc_xtlb_code(void);
     24  void exc_cache_code(void);
     25  void exc_norm_code(void);
     26
     27  memcpy( (void *)T_VEC, exc_tlb_code, 40 );    /* tlbmiss vector */
     28  memcpy( (void *)X_VEC, exc_xtlb_code, 40 );   /* xtlbmiss vector */
     29  memcpy( (void *)C_VEC, exc_cache_code, 40 );  /* cache error vector */
     30  memcpy( (void *)E_VEC, exc_norm_code, 40 );   /* exception vector */
     31
    2132#elif __mips == 3
    2233  void exc_tlb_code(void);
  • c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S

    r7cde240 r74fb4e1f  
    4242
    4343/*
     44 * MIPS ISA Level 32
     45 * XXX Again, reliance on SIM. Not good.??????????
     46 */
     47#elif __mips == 32
     48FRAME(exc_tlb_code,sp,0,ra)
     49        la      k0, _ISR_Handler
     50        j       k0
     51        nop
     52ENDFRAME(exc_tlb_code)
     53
     54FRAME(exc_xtlb_code,sp,0,ra)
     55        la      k0, _ISR_Handler
     56        j       k0
     57        nop
     58
     59ENDFRAME(exc_xtlb_code)
     60
     61FRAME(exc_cache_code,sp,0,ra)
     62        la      k0, _ISR_Handler
     63        j       k0
     64        nop
     65ENDFRAME(exc_cache_code)
     66
     67FRAME(exc_norm_code,sp,0,ra)
     68        la      k0, _ISR_Handler /* generic external int hndlr */
     69        j       k0
     70        nop
     71ENDFRAME(exc_norm_code)
     72       
     73/*
    4474 * MIPS ISA Level 3
    4575 * XXX Again, reliance on SIM. Not good.
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