Index: c/src/lib/libbsp/powerpc/ChangeLog
===================================================================
--- c/src/lib/libbsp/powerpc/ChangeLog	(revision 0fe59ec6d16647a60291efc8219aaf2c49233dd5)
+++ c/src/lib/libbsp/powerpc/ChangeLog	(revision 73cdeb6a514de2310ab01d71ef2cff3155035c52)
@@ -1,2 +1,16 @@
+2007-07-02	Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
+
+	* acinclude.m4, shared/irq/irq_asm.S, shared/irq/irq.c,
+	* shared/vectors/vectors_entry.S, shared/vectors/vectors.h,
+	* shared/vectors/vectors_init.c, shared/vectors/vectors.S:
+	converted various BSP specific implementations into a more general
+	"shared" one
+
+2007-07-02	Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
+
+	* vitex/:
+	integrated "virtex" BSP to support PPC core implemented in a
+	Xilinx virtex FPGA
+
 2007-06-20	Joel Sherrill <joel.sherrill@oarcorp.com>
 
Index: c/src/lib/libbsp/powerpc/acinclude.m4
===================================================================
--- c/src/lib/libbsp/powerpc/acinclude.m4	(revision 0fe59ec6d16647a60291efc8219aaf2c49233dd5)
+++ c/src/lib/libbsp/powerpc/acinclude.m4	(revision 73cdeb6a514de2310ab01d71ef2cff3155035c52)
@@ -25,4 +25,6 @@
   ss555 )
     AC_CONFIG_SUBDIRS([ss555]);;
+  virtex )
+    AC_CONFIG_SUBDIRS([virtex]);;
   *)
     AC_MSG_ERROR([Invalid BSP]);;
Index: c/src/lib/libbsp/powerpc/motorola_powerpc/Makefile.am
===================================================================
--- c/src/lib/libbsp/powerpc/motorola_powerpc/Makefile.am	(revision 0fe59ec6d16647a60291efc8219aaf2c49233dd5)
+++ c/src/lib/libbsp/powerpc/motorola_powerpc/Makefile.am	(revision 73cdeb6a514de2310ab01d71ef2cff3155035c52)
@@ -129,4 +129,5 @@
 vectors_rel_SOURCES = ../../powerpc/shared/vectors/vectors.h \
     ../../powerpc/shared/vectors/vectors_init.c \
+    ../../powerpc/shared/vectors/vectors_entry.S \
     ../../powerpc/shared/vectors/vectors.S
 vectors_rel_CPPFLAGS = $(AM_CPPFLAGS)
@@ -162,9 +163,10 @@
     ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
     ../../../libcpu/@RTEMS_CPU@/mpc6xx/clock.rel \
-    ../../../libcpu/@RTEMS_CPU@/mpc6xx/exceptions.rel \
+    ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
     ../../../libcpu/@RTEMS_CPU@/mpc6xx/mmu.rel \
     ../../../libcpu/@RTEMS_CPU@/mpc6xx/timer.rel
 
 EXTRA_DIST += BOOTING README.mtx603e README.MVME2100 README.MVME2300 \
+              README.MVME2400 \
     README.OTHERBOARDS README.mcp750 README.MVME2307 README.dec21140
 EXTRA_DIST += times.mcp750 times.mvme2307
Index: c/src/lib/libbsp/powerpc/shared/irq/irq.c
===================================================================
--- c/src/lib/libbsp/powerpc/shared/irq/irq.c	(revision 0fe59ec6d16647a60291efc8219aaf2c49233dd5)
+++ c/src/lib/libbsp/powerpc/shared/irq/irq.c	(revision 73cdeb6a514de2310ab01d71ef2cff3155035c52)
@@ -334,5 +334,5 @@
     vectorDesc.off		=	nop_func;
     vectorDesc.isOn		=	connected;
-    if (!mpc60x_set_exception (&vectorDesc)) {
+    if (!ppc_set_exception (&vectorDesc)) {
       BSP_panic("Unable to initialize RTEMS decrementer raw exception\n");
     }
@@ -341,5 +341,5 @@
     vectorDesc.hdl.raw_hdl	=	external_exception_vector_prolog_code;
     vectorDesc.hdl.raw_hdl_size	=	(unsigned) external_exception_vector_prolog_code_size;
-    if (!mpc60x_set_exception (&vectorDesc)) {
+    if (!ppc_set_exception (&vectorDesc)) {
       BSP_panic("Unable to initialize RTEMS external raw exception\n");
     }
Index: c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S
===================================================================
--- c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S	(revision 0fe59ec6d16647a60291efc8219aaf2c49233dd5)
+++ c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S	(revision 73cdeb6a514de2310ab01d71ef2cff3155035c52)
@@ -31,5 +31,5 @@
 	.text
 	.p2align 5
-
+#if defined(ASM_DEC_VECTOR)
 	PUBLIC_VAR(decrementer_exception_vector_prolog_code)
 
@@ -46,7 +46,43 @@
 
 	decrementer_exception_vector_prolog_code_size = . - decrementer_exception_vector_prolog_code
-
+#endif
+
+#if defined(ASM_PIT_VECTOR)
+	PUBLIC_VAR(pit_exception_vector_prolog_code)
+
+SYM (pit_exception_vector_prolog_code):
+	/*
+	 * let room for exception frame
+	 */
+	stwu    r1, - (EXCEPTION_FRAME_END)(r1)
+	stw	r4, GPR4_OFFSET(r1)
+	li	r4, ASM_PIT_VECTOR
+	ba	shared_raw_irq_code_entry
+
+	PUBLIC_VAR (pit_exception_vector_prolog_code_size)
+
+	pit_exception_vector_prolog_code_size = . - pit_exception_vector_prolog_code
+#endif
+
+#if defined(ASM_FIT_VECTOR)
+	PUBLIC_VAR(fit_exception_vector_prolog_code)
+
+SYM (fit_exception_vector_prolog_code):
+	/*
+	 * let room for exception frame
+	 */
+	stwu    r1, - (EXCEPTION_FRAME_END)(r1)
+	stw	r4, GPR4_OFFSET(r1)
+	li	r4, ASM_FIT_VECTOR
+	ba	shared_raw_irq_code_entry
+
+	PUBLIC_VAR (fit_exception_vector_prolog_code_size)
+
+	fit_exception_vector_prolog_code_size = . - fit_exception_vector_prolog_code
+#endif
+	
 	PUBLIC_VAR(external_exception_vector_prolog_code)
 
+#if defined(ASM_EXT_VECTOR)
 SYM (external_exception_vector_prolog_code):
 	/*
@@ -61,4 +97,5 @@
 
 	external_exception_vector_prolog_code_size = . - external_exception_vector_prolog_code
+#endif
 
 	PUBLIC_VAR(shared_raw_irq_code_entry)
@@ -91,10 +128,12 @@
 	stw	r3, SRR1_FRAME_OFFSET(r1)
 
+#if defined(PPC_MSR_EXC_BITS)
 	mfmsr	r3
 	/*
 	 * Enable data and instruction address translation, exception recovery
 	 */
-	ori     r3, r3, MSR_RI | MSR_IR | MSR_DR
+	ori     r3, r3, PPC_MSR_EXC_BITS
 	mtmsr   r3
+#endif
 	SYNC
 	/*
@@ -281,8 +320,10 @@
 	 * Disable data and instruction translation. Make path non recoverable...
 	 */
+#if defined(PPC_MSR_EXC_BITS)
 	mfmsr	r3
-	xori	r3, r3, MSR_RI | MSR_IR | MSR_DR
+	xori	r3, r3, PPC_MSR_EXC_BITS
 	mtmsr   r3
 	SYNC
+#endif
 	/*
 	 * Restore rfi related settings
@@ -332,8 +373,10 @@
 	 * translation.
 	 */
+#if defined(PPC_MSR_EXC_BITS)
 	mfmsr	r3
-	xori	r3, r3, MSR_RI | MSR_IR | MSR_DR
+	xori	r3, r3, PPC_MSR_EXC_BITS
 	mtmsr   r3
 	SYNC
+#endif
 	/*
 	 * Restore rfi related settings
Index: c/src/lib/libbsp/powerpc/shared/vectors/vectors.S
===================================================================
--- c/src/lib/libbsp/powerpc/shared/vectors/vectors.S	(revision 0fe59ec6d16647a60291efc8219aaf2c49233dd5)
+++ c/src/lib/libbsp/powerpc/shared/vectors/vectors.S	(revision 73cdeb6a514de2310ab01d71ef2cff3155035c52)
@@ -13,20 +13,9 @@
 #include <bsp/vectors.h>
 #include <libcpu/raw_exception.h>
-
+		
 #define SYNC \
 	sync; \
 	isync
 
-	PUBLIC_VAR (__rtems_start)
-	.section .entry_point_section,"awx",@progbits
-/*
- * Entry point information used by bootloader code
- */
-SYM (__rtems_start):
-	.long   __rtems_entry_point
-
-	/*
-	 * end of special Entry point section
-	 */
 	.text
 	/* 603e shadows GPR0..GPR3 for certain exceptions. We must switch
@@ -73,7 +62,14 @@
 	 * (256 * vector number) + few instructions
 	 */
+	/*
+	 * FIXME: vectors should distingish
+	 * all bits in mask 0x00003ff0
+	 * and keep in mind that the LR/R3 contains the 
+	 * address BEHIND the entry code 
+	 */
 	mflr	r3
 	/* mask upper bits in case vectors are in the high area (psim) */
 	rlwinm  r3, r3, 32-5, 20, 31
+#if defined(ASM_VEC_VECTOR)
 	/*
 	 * Remap altivec unavaliable (0xf20) to its vector number...
@@ -83,4 +79,5 @@
 	li		r3,ASM_VEC_VECTOR<<3
 1:
+#endif
 	/*
 	 * r3 = r3 >> 8 = vector #
@@ -93,8 +90,25 @@
 	 */
 	stw	r2, GPR2_OFFSET(r1)
+#if defined(ASM_VECTORS_CRITICAL)
+	lis	r0,ASM_VECTORS_CRITICAL@h
+	ori	r0,r0,ASM_VECTORS_CRITICAL@l
+	rlwnm.  r0,r0,r3,0,0
+	beq	1f
+	/*
+	 * NOTE: srr2/3 are stored in slots SRR0/1
+	 * for critical exceptions
+	 */ 
+	mfsrr2  r3
+	stw	r3, SRR0_FRAME_OFFSET(r1)
+	mfsrr3  r3
+	stw	r3, SRR1_FRAME_OFFSET(r1)
+	b	2f
+1:		
+#endif	
 	mfsrr0  r3
 	stw	r3, SRR0_FRAME_OFFSET(r1)
 	mfsrr1  r3
 	stw	r3, SRR1_FRAME_OFFSET(r1)
+2:	
 	/*
 	 * Save general purpose registers
@@ -124,12 +138,14 @@
 	 */
 	stw     r3, GPR1_OFFSET(r1)
+
+#if defined(PPC_MSR_EXC_BITS)
 	/*
 	 * Enable data and instruction address translation, exception nesting
 	 */
 	mfmsr	r3
-	ori     r3,r3, MSR_RI | MSR_IR | MSR_DR
+	ori     r3,r3, PPC_MSR_EXC_BITS
 	mtmsr   r3
 	SYNC
-
+#endif
 	/*
 	 * Call C exception handler
@@ -162,13 +178,43 @@
 	lmw	r4, GPR4_OFFSET(r1)
 	lwz	r2, GPR2_OFFSET(r1)
+
+	/*
+	 * Disable data and instruction translation. Mark path non recoverable
+	 */
+#if defined(PPC_MSR_EXC_BITS)
+	mfmsr	r3
+	xori	r3, r3, PPC_MSR_EXC_BITS
+	mtmsr   r3
+	SYNC
+#endif
+#if defined(ASM_VECTORS_CRITICAL)
+	/*
+	 * determine, whether to restore from
+	 * srr0/1 or srr2/3
+	 */
+	lis	r0,ASM_VECTORS_CRITICAL@h
+	lwz	r3,EXCEPTION_NUMBER_OFFSET(r1)
+	ori	r0,r0,ASM_VECTORS_CRITICAL@l
+	rlwnm.  r0,r0,r3,0,0
+	beq	1f
+	/*
+	 * NOTE: srr2/3 are stored in slots SRR0/1
+	 * for critical exceptions
+	 */ 
+	lwz	r3, SRR1_FRAME_OFFSET(r1)
+	mtsrr3	r3
+	lwz	r3, SRR0_FRAME_OFFSET(r1)
+	mtsrr2	r3
+	lwz	r3, GPR3_OFFSET(r1)
 	lwz	r0, GPR0_OFFSET(r1)
-
-	/*
-	 * Disable data and instruction translation. Make path non recoverable...
-	 */
-	mfmsr	r3
-	xori	r3, r3, MSR_RI | MSR_IR | MSR_DR
-	mtmsr   r3
-	SYNC
+	/* DONT add back the frame size but reload the value
+	 * stored in the frame -- maybe the exception handler
+	 * changed it with good reason (e.g., gdb pushed a dummy frame)
+	 */
+	lwz r1, GPR1_OFFSET(r1)
+	SYNC
+	rfci
+1:		
+#endif	
 	/*
 	 * Restore rfi related settings
@@ -181,4 +227,5 @@
 
 	lwz	r3, GPR3_OFFSET(r1)
+	lwz	r0, GPR0_OFFSET(r1)
 	/* DONT add back the frame size but reload the value
 	 * stored in the frame -- maybe the exception handler
Index: c/src/lib/libbsp/powerpc/shared/vectors/vectors.h
===================================================================
--- c/src/lib/libbsp/powerpc/shared/vectors/vectors.h	(revision 0fe59ec6d16647a60291efc8219aaf2c49233dd5)
+++ c/src/lib/libbsp/powerpc/shared/vectors/vectors.h	(revision 73cdeb6a514de2310ab01d71ef2cff3155035c52)
@@ -13,6 +13,7 @@
  *  $Id$
  */
-#ifndef LIBBSP_POWERPC_MCP750_VECTORS_H
-#define LIBBSP_POWERPC_MCP750_VECTORS_H
+#ifndef LIBBSP_POWERPC_SHARED_VECTORS_H
+#define LIBBSP_POWERPC_SHARED_VECTORS_H
+#include <libcpu/raw_exception.h>
 
 /*
@@ -73,14 +74,24 @@
 /*
  * default raw exception handlers
+ * The "*_size" symbol is generated by the linker; prevent it from
+ * being accessed in one of the short data areas by declaring
+ * it as an array
  */
 
 extern	void default_exception_vector_code_prolog();
+extern	unsigned int  default_exception_vector_code_prolog_size[];
 extern	void tgpr_clr_exception_vector_code_prolog();
-/* This symbol is generated by the linker; prevent it from
- * being accessed in one of the short data areas by declaring
- * it as an array
+extern	unsigned int  tgpr_clr_exception_vector_code_prolog_size[];
+/*
+ * FIXME: these should move to a "irq_asm.h"
  */
-extern	int  default_exception_vector_code_prolog_size[];
-extern	int  tgpr_clr_exception_vector_code_prolog_size[];
+extern  void external_exception_vector_prolog_code();
+extern  unsigned int  external_exception_vector_prolog_code_size[];
+extern  void decrementer_exception_vector_prolog_code();
+extern  unsigned int  decrementer_exception_vector_prolog_code_size[];
+extern  void pit_exception_vector_prolog_code();
+extern  unsigned int  pit_exception_vector_prolog_code_size[];
+extern  void fit_exception_vector_prolog_code();
+extern  unsigned int  fit_exception_vector_prolog_code_size[];
 
 /* codemove is like memmove, but it also gets the cache line size
@@ -92,4 +103,6 @@
  */
 extern void * codemove(void *, const void *, unsigned int, unsigned long);
+extern void exception_nop_enable(const rtems_raw_except_connect_data* ptr);
+extern int  exception_always_enabled(const rtems_raw_except_connect_data* ptr);
 extern void initialize_exceptions();
 
@@ -146,4 +159,10 @@
 typedef exception_handler_t cpuExcHandlerType;
 
+/*
+ * dummy functions for exception interface
+ */
+void exception_nop_enable(const rtems_raw_except_connect_data* ptr);
+int exception_always_enabled(const rtems_raw_except_connect_data* ptr);
+
 #endif /* ASM */
 
Index: c/src/lib/libbsp/powerpc/shared/vectors/vectors_init.c
===================================================================
--- c/src/lib/libbsp/powerpc/shared/vectors/vectors_init.c	(revision 0fe59ec6d16647a60291efc8219aaf2c49233dd5)
+++ c/src/lib/libbsp/powerpc/shared/vectors/vectors_init.c	(revision 73cdeb6a514de2310ab01d71ef2cff3155035c52)
@@ -26,5 +26,4 @@
 static rtems_raw_except_connect_data    exception_table[LAST_VALID_EXC + 1];
 
-extern exception_handler_t globalExceptHdl;
 exception_handler_t globalExceptHdl;
 
@@ -116,4 +115,5 @@
   printk("\t XER = %x\n", excPtr->EXC_XER);
   printk("\t LR = %x\n", excPtr->EXC_LR);
+  printk("\t MSR = %x\n", excPtr->EXC_MSR);
   printk("\t DAR = %x\n", excPtr->EXC_DAR);
 
@@ -134,13 +134,17 @@
 }
 
-void nop_except_enable(const rtems_raw_except_connect_data* ptr)
-{
-}
-int except_always_enabled(const rtems_raw_except_connect_data* ptr)
+/***********************************************************
+ * dummy functions for on/off/isOn calls
+ * these functions just do nothing fulfill the semantic
+ * requirements to enable/disable a certain exception
+ */
+void exception_nop_enable(const rtems_raw_except_connect_data* ptr)
+{
+}
+
+int exception_always_enabled(const rtems_raw_except_connect_data* ptr)
 {
   return 1;
 }
-
-int mpc60x_vector_is_valid(rtems_vector vector);
 
 void initialize_exceptions()
@@ -175,8 +179,9 @@
   }
   for (i=0; i <= exception_config.exceptSize; i++) {
-    if (!mpc60x_vector_is_valid (i)) {
+    if (!ppc_vector_is_valid (i)) {
       continue;
     }
     exception_table[i].exceptIndex	= i;
+#if defined(PPC_HAS_60X_VECTORS)
     if ( has_shadowed_gprs
          && (   ASM_IMISS_VECTOR  == i
@@ -186,12 +191,15 @@
       exception_table[i].hdl.raw_hdl_size = (unsigned)tgpr_clr_exception_vector_code_prolog_size;
     } else {
-      exception_table[i].hdl		  = exception_config.defaultRawEntry.hdl;
+      exception_table[i].hdl		= exception_config.defaultRawEntry.hdl;
     }
+#else
+    exception_table[i].hdl		= exception_config.defaultRawEntry.hdl;
+#endif
     exception_table[i].hdl.vector	= i;
-    exception_table[i].on		= nop_except_enable;
-    exception_table[i].off		= nop_except_enable;
-    exception_table[i].isOn		= except_always_enabled;
-  }
-  if (!mpc60x_init_exceptions(&exception_config)) {
+    exception_table[i].on		= exception_nop_enable;
+    exception_table[i].off		= exception_nop_enable;
+    exception_table[i].isOn		= exception_always_enabled;
+  }
+  if (!ppc_init_exceptions(&exception_config)) {
     BSP_panic("Exception handling initialization failed\n");
   }
