Changeset 73cdeb6 in rtems


Ignore:
Timestamp:
Jul 4, 2007, 12:25:49 PM (12 years ago)
Author:
Thomas Doerfler <Thomas.Doerfler@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
862c2317
Parents:
8bfffd9b
Message:

merged individual exception handler code to a common one.

Files:
20 edited

Legend:

Unmodified
Added
Removed
  • ChangeLog

    r8bfffd9b r73cdeb6  
     12007-07-02      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
     2
     3        * :README.configure: Add virtex BSP
     4
    152007-06-20      Joel Sherrill <joel.sherrill@oarcorp.com>
    26
  • README.configure

    r8bfffd9b r73cdeb6  
    204204                  mbx821_001 mbx821_002 mbx821_002b mbx860_001b
    205205                  mbx860_002 mbx860_005b mtx603e brs5l gen5200 ep5200
     206                  virtex
    206207
    207208                  NOTE: The "motorola_powerpc" BSP is a single BSP which
  • c/src/lib/libbsp/powerpc/ChangeLog

    r8bfffd9b r73cdeb6  
     12007-07-02      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
     2
     3        * acinclude.m4, shared/irq/irq_asm.S, shared/irq/irq.c,
     4        * shared/vectors/vectors_entry.S, shared/vectors/vectors.h,
     5        * shared/vectors/vectors_init.c, shared/vectors/vectors.S:
     6        converted various BSP specific implementations into a more general
     7        "shared" one
     8
     92007-07-02      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
     10
     11        * vitex/:
     12        integrated "virtex" BSP to support PPC core implemented in a
     13        Xilinx virtex FPGA
     14
    1152007-06-20      Joel Sherrill <joel.sherrill@oarcorp.com>
    216
  • c/src/lib/libbsp/powerpc/acinclude.m4

    r8bfffd9b r73cdeb6  
    2525  ss555 )
    2626    AC_CONFIG_SUBDIRS([ss555]);;
     27  virtex )
     28    AC_CONFIG_SUBDIRS([virtex]);;
    2729  *)
    2830    AC_MSG_ERROR([Invalid BSP]);;
  • c/src/lib/libbsp/powerpc/motorola_powerpc/Makefile.am

    r8bfffd9b r73cdeb6  
    129129vectors_rel_SOURCES = ../../powerpc/shared/vectors/vectors.h \
    130130    ../../powerpc/shared/vectors/vectors_init.c \
     131    ../../powerpc/shared/vectors/vectors_entry.S \
    131132    ../../powerpc/shared/vectors/vectors.S
    132133vectors_rel_CPPFLAGS = $(AM_CPPFLAGS)
     
    162163    ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
    163164    ../../../libcpu/@RTEMS_CPU@/mpc6xx/clock.rel \
    164     ../../../libcpu/@RTEMS_CPU@/mpc6xx/exceptions.rel \
     165    ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
    165166    ../../../libcpu/@RTEMS_CPU@/mpc6xx/mmu.rel \
    166167    ../../../libcpu/@RTEMS_CPU@/mpc6xx/timer.rel
    167168
    168169EXTRA_DIST += BOOTING README.mtx603e README.MVME2100 README.MVME2300 \
     170              README.MVME2400 \
    169171    README.OTHERBOARDS README.mcp750 README.MVME2307 README.dec21140
    170172EXTRA_DIST += times.mcp750 times.mvme2307
  • c/src/lib/libbsp/powerpc/shared/irq/irq.c

    r8bfffd9b r73cdeb6  
    334334    vectorDesc.off              =       nop_func;
    335335    vectorDesc.isOn             =       connected;
    336     if (!mpc60x_set_exception (&vectorDesc)) {
     336    if (!ppc_set_exception (&vectorDesc)) {
    337337      BSP_panic("Unable to initialize RTEMS decrementer raw exception\n");
    338338    }
     
    341341    vectorDesc.hdl.raw_hdl      =       external_exception_vector_prolog_code;
    342342    vectorDesc.hdl.raw_hdl_size =       (unsigned) external_exception_vector_prolog_code_size;
    343     if (!mpc60x_set_exception (&vectorDesc)) {
     343    if (!ppc_set_exception (&vectorDesc)) {
    344344      BSP_panic("Unable to initialize RTEMS external raw exception\n");
    345345    }
  • c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S

    r8bfffd9b r73cdeb6  
    3131        .text
    3232        .p2align 5
    33 
     33#if defined(ASM_DEC_VECTOR)
    3434        PUBLIC_VAR(decrementer_exception_vector_prolog_code)
    3535
     
    4646
    4747        decrementer_exception_vector_prolog_code_size = . - decrementer_exception_vector_prolog_code
    48 
     48#endif
     49
     50#if defined(ASM_PIT_VECTOR)
     51        PUBLIC_VAR(pit_exception_vector_prolog_code)
     52
     53SYM (pit_exception_vector_prolog_code):
     54        /*
     55         * let room for exception frame
     56         */
     57        stwu    r1, - (EXCEPTION_FRAME_END)(r1)
     58        stw     r4, GPR4_OFFSET(r1)
     59        li      r4, ASM_PIT_VECTOR
     60        ba      shared_raw_irq_code_entry
     61
     62        PUBLIC_VAR (pit_exception_vector_prolog_code_size)
     63
     64        pit_exception_vector_prolog_code_size = . - pit_exception_vector_prolog_code
     65#endif
     66
     67#if defined(ASM_FIT_VECTOR)
     68        PUBLIC_VAR(fit_exception_vector_prolog_code)
     69
     70SYM (fit_exception_vector_prolog_code):
     71        /*
     72         * let room for exception frame
     73         */
     74        stwu    r1, - (EXCEPTION_FRAME_END)(r1)
     75        stw     r4, GPR4_OFFSET(r1)
     76        li      r4, ASM_FIT_VECTOR
     77        ba      shared_raw_irq_code_entry
     78
     79        PUBLIC_VAR (fit_exception_vector_prolog_code_size)
     80
     81        fit_exception_vector_prolog_code_size = . - fit_exception_vector_prolog_code
     82#endif
     83       
    4984        PUBLIC_VAR(external_exception_vector_prolog_code)
    5085
     86#if defined(ASM_EXT_VECTOR)
    5187SYM (external_exception_vector_prolog_code):
    5288        /*
     
    6197
    6298        external_exception_vector_prolog_code_size = . - external_exception_vector_prolog_code
     99#endif
    63100
    64101        PUBLIC_VAR(shared_raw_irq_code_entry)
     
    91128        stw     r3, SRR1_FRAME_OFFSET(r1)
    92129
     130#if defined(PPC_MSR_EXC_BITS)
    93131        mfmsr   r3
    94132        /*
    95133         * Enable data and instruction address translation, exception recovery
    96134         */
    97         ori     r3, r3, MSR_RI | MSR_IR | MSR_DR
     135        ori     r3, r3, PPC_MSR_EXC_BITS
    98136        mtmsr   r3
     137#endif
    99138        SYNC
    100139        /*
     
    281320         * Disable data and instruction translation. Make path non recoverable...
    282321         */
     322#if defined(PPC_MSR_EXC_BITS)
    283323        mfmsr   r3
    284         xori    r3, r3, MSR_RI | MSR_IR | MSR_DR
     324        xori    r3, r3, PPC_MSR_EXC_BITS
    285325        mtmsr   r3
    286326        SYNC
     327#endif
    287328        /*
    288329         * Restore rfi related settings
     
    332373         * translation.
    333374         */
     375#if defined(PPC_MSR_EXC_BITS)
    334376        mfmsr   r3
    335         xori    r3, r3, MSR_RI | MSR_IR | MSR_DR
     377        xori    r3, r3, PPC_MSR_EXC_BITS
    336378        mtmsr   r3
    337379        SYNC
     380#endif
    338381        /*
    339382         * Restore rfi related settings
  • c/src/lib/libbsp/powerpc/shared/vectors/vectors.S

    r8bfffd9b r73cdeb6  
    1313#include <bsp/vectors.h>
    1414#include <libcpu/raw_exception.h>
    15 
     15               
    1616#define SYNC \
    1717        sync; \
    1818        isync
    1919
    20         PUBLIC_VAR (__rtems_start)
    21         .section .entry_point_section,"awx",@progbits
    22 /*
    23  * Entry point information used by bootloader code
    24  */
    25 SYM (__rtems_start):
    26         .long   __rtems_entry_point
    27 
    28         /*
    29          * end of special Entry point section
    30          */
    3120        .text
    3221        /* 603e shadows GPR0..GPR3 for certain exceptions. We must switch
     
    7362         * (256 * vector number) + few instructions
    7463         */
     64        /*
     65         * FIXME: vectors should distingish
     66         * all bits in mask 0x00003ff0
     67         * and keep in mind that the LR/R3 contains the
     68         * address BEHIND the entry code
     69         */
    7570        mflr    r3
    7671        /* mask upper bits in case vectors are in the high area (psim) */
    7772        rlwinm  r3, r3, 32-5, 20, 31
     73#if defined(ASM_VEC_VECTOR)
    7874        /*
    7975         * Remap altivec unavaliable (0xf20) to its vector number...
     
    8379        li              r3,ASM_VEC_VECTOR<<3
    84801:
     81#endif
    8582        /*
    8683         * r3 = r3 >> 8 = vector #
     
    9390         */
    9491        stw     r2, GPR2_OFFSET(r1)
     92#if defined(ASM_VECTORS_CRITICAL)
     93        lis     r0,ASM_VECTORS_CRITICAL@h
     94        ori     r0,r0,ASM_VECTORS_CRITICAL@l
     95        rlwnm.  r0,r0,r3,0,0
     96        beq     1f
     97        /*
     98         * NOTE: srr2/3 are stored in slots SRR0/1
     99         * for critical exceptions
     100         */
     101        mfsrr2  r3
     102        stw     r3, SRR0_FRAME_OFFSET(r1)
     103        mfsrr3  r3
     104        stw     r3, SRR1_FRAME_OFFSET(r1)
     105        b       2f
     1061:             
     107#endif 
    95108        mfsrr0  r3
    96109        stw     r3, SRR0_FRAME_OFFSET(r1)
    97110        mfsrr1  r3
    98111        stw     r3, SRR1_FRAME_OFFSET(r1)
     1122:     
    99113        /*
    100114         * Save general purpose registers
     
    124138         */
    125139        stw     r3, GPR1_OFFSET(r1)
     140
     141#if defined(PPC_MSR_EXC_BITS)
    126142        /*
    127143         * Enable data and instruction address translation, exception nesting
    128144         */
    129145        mfmsr   r3
    130         ori     r3,r3, MSR_RI | MSR_IR | MSR_DR
     146        ori     r3,r3, PPC_MSR_EXC_BITS
    131147        mtmsr   r3
    132148        SYNC
    133 
     149#endif
    134150        /*
    135151         * Call C exception handler
     
    162178        lmw     r4, GPR4_OFFSET(r1)
    163179        lwz     r2, GPR2_OFFSET(r1)
     180
     181        /*
     182         * Disable data and instruction translation. Mark path non recoverable
     183         */
     184#if defined(PPC_MSR_EXC_BITS)
     185        mfmsr   r3
     186        xori    r3, r3, PPC_MSR_EXC_BITS
     187        mtmsr   r3
     188        SYNC
     189#endif
     190#if defined(ASM_VECTORS_CRITICAL)
     191        /*
     192         * determine, whether to restore from
     193         * srr0/1 or srr2/3
     194         */
     195        lis     r0,ASM_VECTORS_CRITICAL@h
     196        lwz     r3,EXCEPTION_NUMBER_OFFSET(r1)
     197        ori     r0,r0,ASM_VECTORS_CRITICAL@l
     198        rlwnm.  r0,r0,r3,0,0
     199        beq     1f
     200        /*
     201         * NOTE: srr2/3 are stored in slots SRR0/1
     202         * for critical exceptions
     203         */
     204        lwz     r3, SRR1_FRAME_OFFSET(r1)
     205        mtsrr3  r3
     206        lwz     r3, SRR0_FRAME_OFFSET(r1)
     207        mtsrr2  r3
     208        lwz     r3, GPR3_OFFSET(r1)
    164209        lwz     r0, GPR0_OFFSET(r1)
    165 
    166         /*
    167          * Disable data and instruction translation. Make path non recoverable...
    168          */
    169         mfmsr   r3
    170         xori    r3, r3, MSR_RI | MSR_IR | MSR_DR
    171         mtmsr   r3
    172         SYNC
     210        /* DONT add back the frame size but reload the value
     211         * stored in the frame -- maybe the exception handler
     212         * changed it with good reason (e.g., gdb pushed a dummy frame)
     213         */
     214        lwz r1, GPR1_OFFSET(r1)
     215        SYNC
     216        rfci
     2171:             
     218#endif 
    173219        /*
    174220         * Restore rfi related settings
     
    181227
    182228        lwz     r3, GPR3_OFFSET(r1)
     229        lwz     r0, GPR0_OFFSET(r1)
    183230        /* DONT add back the frame size but reload the value
    184231         * stored in the frame -- maybe the exception handler
  • c/src/lib/libbsp/powerpc/shared/vectors/vectors.h

    r8bfffd9b r73cdeb6  
    1313 *  $Id$
    1414 */
    15 #ifndef LIBBSP_POWERPC_MCP750_VECTORS_H
    16 #define LIBBSP_POWERPC_MCP750_VECTORS_H
     15#ifndef LIBBSP_POWERPC_SHARED_VECTORS_H
     16#define LIBBSP_POWERPC_SHARED_VECTORS_H
     17#include <libcpu/raw_exception.h>
    1718
    1819/*
     
    7374/*
    7475 * default raw exception handlers
     76 * The "*_size" symbol is generated by the linker; prevent it from
     77 * being accessed in one of the short data areas by declaring
     78 * it as an array
    7579 */
    7680
    7781extern  void default_exception_vector_code_prolog();
     82extern  unsigned int  default_exception_vector_code_prolog_size[];
    7883extern  void tgpr_clr_exception_vector_code_prolog();
    79 /* This symbol is generated by the linker; prevent it from
    80  * being accessed in one of the short data areas by declaring
    81  * it as an array
     84extern  unsigned int  tgpr_clr_exception_vector_code_prolog_size[];
     85/*
     86 * FIXME: these should move to a "irq_asm.h"
    8287 */
    83 extern  int  default_exception_vector_code_prolog_size[];
    84 extern  int  tgpr_clr_exception_vector_code_prolog_size[];
     88extern  void external_exception_vector_prolog_code();
     89extern  unsigned int  external_exception_vector_prolog_code_size[];
     90extern  void decrementer_exception_vector_prolog_code();
     91extern  unsigned int  decrementer_exception_vector_prolog_code_size[];
     92extern  void pit_exception_vector_prolog_code();
     93extern  unsigned int  pit_exception_vector_prolog_code_size[];
     94extern  void fit_exception_vector_prolog_code();
     95extern  unsigned int  fit_exception_vector_prolog_code_size[];
    8596
    8697/* codemove is like memmove, but it also gets the cache line size
     
    92103 */
    93104extern void * codemove(void *, const void *, unsigned int, unsigned long);
     105extern void exception_nop_enable(const rtems_raw_except_connect_data* ptr);
     106extern int  exception_always_enabled(const rtems_raw_except_connect_data* ptr);
    94107extern void initialize_exceptions();
    95108
     
    146159typedef exception_handler_t cpuExcHandlerType;
    147160
     161/*
     162 * dummy functions for exception interface
     163 */
     164void exception_nop_enable(const rtems_raw_except_connect_data* ptr);
     165int exception_always_enabled(const rtems_raw_except_connect_data* ptr);
     166
    148167#endif /* ASM */
    149168
  • c/src/lib/libbsp/powerpc/shared/vectors/vectors_init.c

    r8bfffd9b r73cdeb6  
    2626static rtems_raw_except_connect_data    exception_table[LAST_VALID_EXC + 1];
    2727
    28 extern exception_handler_t globalExceptHdl;
    2928exception_handler_t globalExceptHdl;
    3029
     
    116115  printk("\t XER = %x\n", excPtr->EXC_XER);
    117116  printk("\t LR = %x\n", excPtr->EXC_LR);
     117  printk("\t MSR = %x\n", excPtr->EXC_MSR);
    118118  printk("\t DAR = %x\n", excPtr->EXC_DAR);
    119119
     
    134134}
    135135
    136 void nop_except_enable(const rtems_raw_except_connect_data* ptr)
    137 {
    138 }
    139 int except_always_enabled(const rtems_raw_except_connect_data* ptr)
     136/***********************************************************
     137 * dummy functions for on/off/isOn calls
     138 * these functions just do nothing fulfill the semantic
     139 * requirements to enable/disable a certain exception
     140 */
     141void exception_nop_enable(const rtems_raw_except_connect_data* ptr)
     142{
     143}
     144
     145int exception_always_enabled(const rtems_raw_except_connect_data* ptr)
    140146{
    141147  return 1;
    142148}
    143 
    144 int mpc60x_vector_is_valid(rtems_vector vector);
    145149
    146150void initialize_exceptions()
     
    175179  }
    176180  for (i=0; i <= exception_config.exceptSize; i++) {
    177     if (!mpc60x_vector_is_valid (i)) {
     181    if (!ppc_vector_is_valid (i)) {
    178182      continue;
    179183    }
    180184    exception_table[i].exceptIndex      = i;
     185#if defined(PPC_HAS_60X_VECTORS)
    181186    if ( has_shadowed_gprs
    182187         && (   ASM_IMISS_VECTOR  == i
     
    186191      exception_table[i].hdl.raw_hdl_size = (unsigned)tgpr_clr_exception_vector_code_prolog_size;
    187192    } else {
    188       exception_table[i].hdl              = exception_config.defaultRawEntry.hdl;
     193      exception_table[i].hdl            = exception_config.defaultRawEntry.hdl;
    189194    }
     195#else
     196    exception_table[i].hdl              = exception_config.defaultRawEntry.hdl;
     197#endif
    190198    exception_table[i].hdl.vector       = i;
    191     exception_table[i].on               = nop_except_enable;
    192     exception_table[i].off              = nop_except_enable;
    193     exception_table[i].isOn             = except_always_enabled;
    194   }
    195   if (!mpc60x_init_exceptions(&exception_config)) {
     199    exception_table[i].on               = exception_nop_enable;
     200    exception_table[i].off              = exception_nop_enable;
     201    exception_table[i].isOn             = exception_always_enabled;
     202  }
     203  if (!ppc_init_exceptions(&exception_config)) {
    196204    BSP_panic("Exception handling initialization failed\n");
    197205  }
  • c/src/lib/libcpu/powerpc/ChangeLog

    r8bfffd9b r73cdeb6  
     12007-07-02      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
     2
     3        * ppc403/clock/clock.c, ppc403/console/console405.c,
     4        * ppc403/irq/ictrl.c, ppc403/irq/ictrl.h, ppc403/tty_drv/tty_drv.c:
     5        Adapted from old to new exception handling to prepare the "virtex" BSP
     6       
     72007-07-02      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
     8
     9        * Makefile.am, preinstall.am, new-exceptions/asm_utils.S,
     10        * new-exceptions/raw_exception.c, new-exceptions/raw_exception.h,
     11        * rtems/powerpc/powerpc.h, shared/include/cpuIdent.c shared/include/cpuIdent.h:
     12        Created a shared implementation of the PowerPC exception
     13        code. These files are a "superset" version of the various
     14        implementations that was available up to now.
     15       
    1162007-05-21      Joel Sherrill <joel.sherrill@oarcorp.com>
    217
  • c/src/lib/libcpu/powerpc/Makefile.am

    r8bfffd9b r73cdeb6  
    3333new_exceptions_rtems_cpu_rel_CPPFLAGS = $(AM_CPPFLAGS)
    3434new_exceptions_rtems_cpu_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
     35
     36
     37include_libcpu_HEADERS += new-exceptions/raw_exception.h
     38noinst_PROGRAMS += new-exceptions/raw_exception.rel
     39new_exceptions_raw_exception_rel_SOURCES = new-exceptions/raw_exception.c \
     40    new-exceptions/asm_utils.S
     41new_exceptions_raw_exception_rel_CPPFLAGS = $(AM_CPPFLAGS)
     42new_exceptions_raw_exception_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
     43
    3544endif
    3645
     
    8594ppc403_console_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
    8695
     96if OLD_EXCEPTIONS
    8797## ppc403/ictrl
    8898include_HEADERS = ppc403/ictrl/ictrl.h
    89 
     99else
     100include_HEADERS =
     101include_libcpu_HEADERS += shared/include/spr.h
     102
     103noinst_PROGRAMS += shared/cpuIdent.rel
     104shared_cpuIdent_rel_SOURCES = shared/include/cpuIdent.c shared/include/cpuIdent.h
     105shared_cpuIdent_rel_CPPFLAGS = $(AM_CPPFLAGS)
     106shared_cpuIdent_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
     107include_libcpu_HEADERS += shared/include/cpuIdent.h
     108
     109endif
     110
     111if OLD_EXCEPTIONS
    90112noinst_PROGRAMS += ppc403/ictrl.rel
    91113ppc403_ictrl_rel_SOURCES = ppc403/ictrl/ictrl.c ppc403/ictrl/ictrl.h
    92114ppc403_ictrl_rel_CPPFLAGS = $(AM_CPPFLAGS)
    93115ppc403_ictrl_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
     116endif
    94117
    95118## ppc403/timer
     
    109132endif
    110133
     134if OLD_EXCEPTIONS
    111135## ppc403/vectors
    112136noinst_PROGRAMS += ppc403/vectors.rel
     
    115139ppc403_vectors_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
    116140endif
     141endif
    117142
    118143EXTRA_DIST += mpc5xx/README
     
    190215
    191216if mpc6xx
    192 include_libcpu_HEADERS += mpc6xx/exceptions/raw_exception.h
    193 
    194 ## mpc6xx/exceptions
    195 noinst_PROGRAMS += mpc6xx/exceptions.rel
    196 mpc6xx_exceptions_rel_SOURCES = mpc6xx/exceptions/raw_exception.c \
    197     mpc6xx/exceptions/asm_utils.S
    198 mpc6xx_exceptions_rel_CPPFLAGS = $(AM_CPPFLAGS)
    199 mpc6xx_exceptions_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
    200217
    201218## mpc6xx/mmu
     
    252269mpc8xx_cpm_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
    253270
    254 ## mpc8xx/exceptions
    255 include_libcpu_HEADERS += mpc8xx/exceptions/raw_exception.h
    256 
    257 noinst_PROGRAMS += mpc8xx/exceptions.rel
    258 mpc8xx_exceptions_rel_SOURCES = mpc8xx/exceptions/raw_exception.c \
    259     mpc8xx/exceptions/asm_utils.S
    260 mpc8xx_exceptions_rel_CPPFLAGS = $(AM_CPPFLAGS)
    261 mpc8xx_exceptions_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
    262 
    263271## mpc8xx/mmu
    264272include_mpc8xx_HEADERS += mpc8xx/include/mmu.h
     
    306314mpc8260_cpm_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
    307315
    308 ## mpc8260/exceptions
    309 include_libcpu_HEADERS += mpc8260/exceptions/raw_exception.h
    310 
    311 noinst_PROGRAMS += mpc8260/exceptions.rel
    312 mpc8260_exceptions_rel_SOURCES = mpc8260/exceptions/raw_exception.c \
    313     mpc8260/exceptions/asm_utils.S \
    314     mpc8260/exceptions/raw_exception.h
    315 mpc8260_exceptions_rel_CPPFLAGS = $(AM_CPPFLAGS)
    316 mpc8260_exceptions_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
    317 
    318316## mpc8260/mmu
    319317include_mpc8260_HEADERS += mpc8260/include/mmu.h
  • c/src/lib/libcpu/powerpc/ppc403/clock/clock.c

    r8bfffd9b r73cdeb6  
    4141#include <rtems/clockdrv.h>
    4242#include <rtems/libio.h>
    43 
    4443#include <stdlib.h>                     /* for atexit() */
     44#include <rtems/bspIo.h>
     45/*
     46 * check, which exception handling code is present
     47 */
     48#if !defined(ppc405)
     49#define PPC_HAS_CLASSIC_EXCEPTIONS TRUE
     50#else
     51#define PPC_HAS_CLASSIC_EXCEPTIONS FALSE
     52#include <bsp/irq.h>
     53#endif
    4554
    4655volatile uint32_t   Clock_driver_ticks;
     
    7988 *  ISR Handler
    8089 */
    81  
    82 rtems_isr
    83 Clock_isr(rtems_vector_number vector)
    84 {
    85       uint32_t   clicks_til_next_interrupt;
     90
     91#if PPC_HAS_CLASSIC_EXCEPTIONS
     92rtems_isr Clock_isr(rtems_vector_number vector)
     93#else
     94void Clock_isr(void* handle)
     95#endif
     96{
     97    uint32_t   clicks_til_next_interrupt;
    8698    if (!auto_restart)
    8799    {
     
    139151}
    140152
    141 void Install_clock(rtems_isr_entry clock_isr)
    142 {
    143     rtems_isr_entry previous_isr;
     153#if !PPC_HAS_CLASSIC_EXCEPTIONS
     154int ClockIsOn(const rtems_irq_connect_data* unused)
     155{
     156    register uint32_t   tcr;
     157 
     158    asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
     159 
     160    return (tcr & 0x04000000) != 0;
     161}
     162#endif
     163
     164void ClockOff(
     165#if PPC_HAS_CLASSIC_EXCEPTIONS
     166              void
     167#else
     168              const rtems_irq_connect_data* unused
     169#endif
     170              )
     171{
     172    register uint32_t   tcr;
     173 
     174    asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
     175 
     176    tcr &= ~ 0x04400000;
     177 
     178    asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
     179}
     180
     181void ClockOn(
     182#if PPC_HAS_CLASSIC_EXCEPTIONS
     183              void
     184#else
     185              const rtems_irq_connect_data* unused
     186#endif
     187              )
     188{
    144189    uint32_t   iocr;
    145190    register uint32_t   tcr;
     
    193238    pit_value = rtems_configuration_get_microseconds_per_tick() *
    194239      rtems_cpu_configuration_get_clicks_per_usec();
     240 
     241     /*
     242      * Set PIT value
     243      */
     244
     245    asm volatile ("mtspr 0x3db, %0" : : "r" (pit_value)); /* PIT */
     246 
     247     /*     
     248      * Set timer to autoreload, bit TCR->ARE = 1  0x0400000
     249      * Enable PIT interrupt, bit TCR->PIE = 1     0x4000000
     250      */
     251    tick_time = get_itimer() + pit_value;
     252
     253    asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
     254    tcr = (tcr & ~0x04400000) | (auto_restart ? 0x04400000 : 0x04000000);
     255#if 1
     256    asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
     257#endif
     258
     259}
     260
     261
     262
     263void Install_clock(
     264#if PPC_HAS_CLASSIC_EXCEPTIONS
     265                   rtems_isr_entry clock_isr
     266#else
     267                   void (*clock_isr)(void *)
     268#endif
     269                   )
     270{
     271#ifdef ppc403
     272    uint32_t   pvr;
     273#endif /* ppc403 */
     274 
     275    Clock_driver_ticks = 0;
    195276 
    196277    /*
     
    202283     */
    203284
     285#if PPC_HAS_CLASSIC_EXCEPTIONS
     286 {
     287    rtems_isr_entry previous_isr;
    204288    rtems_interrupt_catch(clock_isr, PPC_IRQ_PIT, &previous_isr);
    205 
    206      /*
    207       * Set PIT value
    208       */
    209 
    210     asm volatile ("mtspr 0x3db, %0" : : "r" (pit_value)); /* PIT */
    211  
    212      /*     
    213       * Set timer to autoreload, bit TCR->ARE = 1  0x0400000
    214       * Enable PIT interrupt, bit TCR->PIE = 1     0x4000000
    215       */
    216     tick_time = get_itimer() + pit_value;
    217     asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
    218     tcr = (tcr & ~0x04400000) | (auto_restart ? 0x04400000 : 0x04000000);
    219     asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
    220 
     289    ClockOn();
     290 }
     291#else
     292 {
     293   rtems_irq_connect_data clockIrqConnData;
     294   clockIrqConnData.on   = ClockOn;
     295   clockIrqConnData.off  = ClockOff;
     296   clockIrqConnData.isOn = ClockIsOn;
     297   clockIrqConnData.name = BSP_PIT;
     298   clockIrqConnData.hdl  = clock_isr;
     299   if (!BSP_install_rtems_irq_handler (&clockIrqConnData)) {
     300     printk("Unable to connect Clock Irq handler\n");
     301     rtems_fatal_error_occurred(1);
     302   }
     303 }
     304#endif
    221305    atexit(Clock_exit);
    222306}
    223307
    224308void
    225 ReInstall_clock(rtems_isr_entry new_clock_isr)
    226 {
    227     rtems_isr_entry previous_isr;
    228     uint32_t   isrlevel = 0;
    229 
    230     rtems_interrupt_disable(isrlevel);
     309ReInstall_clock(
     310#if PPC_HAS_CLASSIC_EXCEPTIONS
     311                rtems_isr_entry new_clock_isr
     312#else
     313                void (*new_clock_isr)(void *)
     314#endif
     315)
     316{
     317  uint32_t   isrlevel = 0;
     318 
     319  rtems_interrupt_disable(isrlevel);
     320 
     321#if PPC_HAS_CLASSIC_EXCEPTIONS
     322 {
     323   rtems_isr_entry previous_isr;
     324   rtems_interrupt_catch(new_clock_isr, PPC_IRQ_PIT, &previous_isr);
     325   ClockOn();
     326 }
     327#else
     328  {
     329    rtems_irq_connect_data clockIrqConnData;
    231330   
    232     rtems_interrupt_catch(new_clock_isr, PPC_IRQ_PIT, &previous_isr);
    233 
    234     rtems_interrupt_enable(isrlevel);
     331    clockIrqConnData.name = BSP_PIT;
     332    if (!BSP_get_current_rtems_irq_handler(&clockIrqConnData)) {
     333      printk("Unable to stop system clock\n");
     334      rtems_fatal_error_occurred(1);
     335    }
     336   
     337    BSP_remove_rtems_irq_handler (&clockIrqConnData);
     338   
     339    clockIrqConnData.on   = ClockOn;
     340    clockIrqConnData.off  = ClockOff;
     341    clockIrqConnData.isOn = ClockIsOn;
     342    clockIrqConnData.name = BSP_PIT;
     343    clockIrqConnData.hdl  = new_clock_isr;
     344
     345    if (!BSP_install_rtems_irq_handler (&clockIrqConnData)) {
     346      printk("Unable to connect Clock Irq handler\n");
     347      rtems_fatal_error_occurred(1);
     348    }
     349  }
     350#endif
     351
     352  rtems_interrupt_enable(isrlevel);
    235353}
    236354
     
    244362 */
    245363
    246 void
    247 Clock_exit(void)
    248 {
    249     register uint32_t   tcr;
    250  
    251     asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
    252  
    253     tcr &= ~ 0x04400000;
    254  
    255     asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
    256  
    257     (void) set_vector(0, PPC_IRQ_PIT, 1);
     364void Clock_exit(void)
     365{
     366#if PPC_HAS_CLASSIC_EXCEPTIONS
     367  ClockOff();
     368 
     369  (void) set_vector(0, PPC_IRQ_PIT, 1);
     370#else
     371 {
     372    rtems_irq_connect_data clockIrqConnData;
     373   
     374    clockIrqConnData.name = BSP_PIT;
     375    if (!BSP_get_current_rtems_irq_handler(&clockIrqConnData)) {
     376      printk("Unable to stop system clock\n");
     377      rtems_fatal_error_occurred(1);
     378    }
     379   
     380    BSP_remove_rtems_irq_handler (&clockIrqConnData);
     381 }
     382#endif
    258383}
    259384
     
    294419    if (args->command == rtems_build_name('I', 'S', 'R', ' '))
    295420    {
     421#if PPC_HAS_CLASSIC_EXCEPTIONS
    296422        Clock_isr(PPC_IRQ_PIT);
     423#else
     424        Clock_isr(NULL);
     425#endif
    297426    }
    298427    else if (args->command == rtems_build_name('N', 'E', 'W', ' '))
  • c/src/lib/libcpu/powerpc/ppc403/console/console405.c

    r8bfffd9b r73cdeb6  
    160160+---------------------------------------------------------------------------*/
    161161  unsigned char MSR;    /* 0x06 */
    162   #define MSR_DCTS               0x01
    163   #define MSR_DDSR               0x02
    164   #define MSR_TERI               0x04
    165   #define MSR_DDCD               0x08
    166   #define MSR_CTS                0x10
    167   #define MSR_DSR                0x20
    168   #define MSR_RI                 0x40
    169   #define MSR_CD                 0x80
     162  #define UART_MSR_DCTS          0x01
     163  #define UART_MSR_DDSR          0x02
     164  #define UART_MSR_TERI          0x04
     165  #define UART_MSR_DDCD          0x08
     166  #define UART_MSR_CTS           0x10
     167  #define UART_MSR_DSR           0x20
     168  #define UART_MSR_RI            0x40
     169  #define UART_MSR_CD            0x80
    170170
    171171/*---------------------------------------------------------------------------+
  • c/src/lib/libcpu/powerpc/ppc403/tty_drv/tty_drv.c

    r8bfffd9b r73cdeb6  
    118118+---------------------------------------------------------------------------*/
    119119  unsigned char MSR;    /* 0x06 */
    120   #define MSR_DCTS               0x01
    121   #define MSR_DDSR               0x02
    122   #define MSR_TERI               0x04
    123   #define MSR_DDCD               0x08
    124   #define MSR_CTS                0x10
    125   #define MSR_DSR                0x20
    126   #define MSR_RI                 0x40
    127   #define MSR_CD                 0x80
     120  #define UART_MSR_DCTS          0x01
     121  #define UART_MSR_DDSR          0x02
     122  #define UART_MSR_TERI          0x04
     123  #define UART_MSR_DDCD          0x08
     124  #define UART_MSR_CTS           0x10
     125  #define UART_MSR_DSR           0x20
     126  #define UART_MSR_RI            0x40
     127  #define UART_MSR_CD            0x80
    128128
    129129/*---------------------------------------------------------------------------+
  • c/src/lib/libcpu/powerpc/preinstall.am

    r8bfffd9b r73cdeb6  
    5050        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/ppc_offs.h
    5151PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/ppc_offs.h
     52
     53else
     54$(PROJECT_INCLUDE)/libcpu/raw_exception.h: new-exceptions/raw_exception.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
     55        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/raw_exception.h
     56PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/raw_exception.h
    5257endif
    5358if shared
     
    8994endif
    9095if ppc403
     96if OLD_EXCEPTIONS
    9197$(PROJECT_INCLUDE)/ictrl.h: ppc403/ictrl/ictrl.h $(PROJECT_INCLUDE)/$(dirstamp)
    9298        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/ictrl.h
    9399PREINSTALL_FILES += $(PROJECT_INCLUDE)/ictrl.h
    94100
     101else
     102$(PROJECT_INCLUDE)/libcpu/spr.h: shared/include/spr.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
     103        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/spr.h
     104PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/spr.h
     105
     106$(PROJECT_INCLUDE)/libcpu/cpuIdent.h: shared/include/cpuIdent.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
     107        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/cpuIdent.h
     108PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/cpuIdent.h
     109endif
    95110if ppc405
    96111$(PROJECT_INCLUDE)/tty_drv.h: ppc403/tty_drv/tty_drv.h $(PROJECT_INCLUDE)/$(dirstamp)
     
    131146endif
    132147if mpc6xx
    133 $(PROJECT_INCLUDE)/libcpu/raw_exception.h: mpc6xx/exceptions/raw_exception.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
    134         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/raw_exception.h
    135 PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/raw_exception.h
    136 
    137148$(PROJECT_INCLUDE)/libcpu/bat.h: mpc6xx/mmu/bat.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
    138149        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/bat.h
     
    165176PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc8xx/cpm.h
    166177
    167 $(PROJECT_INCLUDE)/libcpu/raw_exception.h: mpc8xx/exceptions/raw_exception.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
    168         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/raw_exception.h
    169 PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/raw_exception.h
    170 
    171178$(PROJECT_INCLUDE)/mpc8xx/mmu.h: mpc8xx/include/mmu.h $(PROJECT_INCLUDE)/mpc8xx/$(dirstamp)
    172179        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc8xx/mmu.h
     
    191198PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc8260/cpm.h
    192199
    193 $(PROJECT_INCLUDE)/libcpu/raw_exception.h: mpc8260/exceptions/raw_exception.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
    194         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/raw_exception.h
    195 PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/raw_exception.h
    196 
    197200$(PROJECT_INCLUDE)/mpc8260/mmu.h: mpc8260/include/mmu.h $(PROJECT_INCLUDE)/mpc8260/$(dirstamp)
    198201        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc8260/mmu.h
  • c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h

    r8bfffd9b r73cdeb6  
    109109#endif
    110110#define PPC_CACHE_ALIGNMENT     16
     111#define PPC_HAS_RI              0
    111112#define PPC_HAS_RFCI            1
    112113#define PPC_USE_MULTIPLE        1
     
    362363#ifndef PPC_HAS_EXCEPTION_PREFIX
    363364#define PPC_HAS_EXCEPTION_PREFIX 1
     365#endif
     366/*
     367 *  Unless otherwise specified, assume the model has an RI bit to
     368 *  identify non-recoverable interrupts
     369 */
     370
     371#ifndef PPC_HAS_RI
     372#define PPC_HAS_RI 1
    364373#endif
    365374
     
    658667 */
    659668
     669#if PPC_HAS_RI
     670#define PPC_MSR_RI       0x000000002 /* bit 30 - recoverable exception */
     671#endif
     672
     673#define PPC_MSR_DR       0x000000010 /* bit 27 - data address translation */
     674#define PPC_MSR_IR       0x000000020 /* bit 26 - instruction addr translation*/
     675
    660676/*
    661677 *  Some PPC model manuals refer to the Exception Prefix (EP) bit as
    662678 *  IP for no apparent reason.
    663679 */
    664 
    665 #define PPC_MSR_RI       0x000000002 /* bit 30 - recoverable exception */
    666 #define PPC_MSR_DR       0x000000010 /* bit 27 - data address translation */
    667 #define PPC_MSR_IR       0x000000020 /* bit 26 - instruction addr translation*/
    668 
    669680#if (PPC_HAS_EXCEPTION_PREFIX)
    670681#define PPC_MSR_EP       0x000000040 /* bit 25 - exception prefix */
     
    709720#endif
    710721
    711 #endif /* _RTEMS_SCORE_POWERPC_H */
     722#endif /* _RTEMS_POWERPC_POWERPC_H */
  • c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c

    r8bfffd9b r73cdeb6  
    3030{
    3131  switch (cpu) {
     32    case PPC_405:               return "PPC405";
    3233    case PPC_601:               return "MPC601";
    3334    case PPC_5XX:               return "MPC5XX";
     
    3839    case PPC_7400:              return "MPC7400";
    3940    case PPC_7455:              return "MPC7455";
    40     case PPC_7457:      return "MPC7457";
     41    case PPC_7457:              return "MPC7457";
    4142    case PPC_603le:             return "MPC603le";
    4243    case PPC_604e:              return "MPC604e";
     
    5960  current_ppc_cpu = (ppc_cpu_id_t) pvr;
    6061  switch (pvr) {
     62    case PPC_405:
    6163    case PPC_601:
    6264    case PPC_5XX:
     
    6971    case PPC_7400:
    7072    case PPC_7455:
    71         case PPC_7457:
     73    case PPC_7457:
    7274    case PPC_604e:
    7375    case PPC_620:
  • c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h

    r8bfffd9b r73cdeb6  
    3030  PPC_604r = 0xA,
    3131  PPC_7400 = 0xC,
     32  PPC_405  = 0x2001,
    3233  PPC_7455 = 0x8001, /* Kate Feng */
    3334  PPC_7457 = 0x8002,
  • make/ChangeLog

    r8bfffd9b r73cdeb6  
     12007-07-02      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
     2
     3        * custom/vitex.cfg: added file to support PPC core in a xilinx
     4        virtex FPGA
     5       
    162007-06-21      Joel Sherrill <joel.sherrill@OARcorp.com>
    27
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