Ignore:
Timestamp:
Mar 24, 1998, 5:10:44 PM (23 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
bdac86b5
Parents:
d662fef8
Message:

Corrected register constraints per suggestion from Thomas Doerfler, IMD
<td@…>.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/powerpc/cpu.h

    rd662fef8 r72b397a  
    619619    asm volatile ( \
    620620        "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
    621         "=r" ((_isr_cookie)) : "r" ((PPC_MSR_DISABLE_MASK)) \
     621        "=&r" ((_isr_cookie)) : "r" ((PPC_MSR_DISABLE_MASK)) \
    622622        ); \
    623623  }
     
    632632  { \
    633633     asm volatile ( "mtmsr %0" : \
    634                    "=r" ((_isr_cookie)) : "0" ((_isr_cookie))); \
     634                   "=&r" ((_isr_cookie)) : "0" ((_isr_cookie))); \
    635635  }
    636636
     
    10161016               "rlwimi %0,%1,8,8,15;"
    10171017               "rlwimi %0,%1,24,0,7;" :
    1018                "=r" ((swapped)) : "r" ((value)));
     1018               "=&r" ((swapped)) : "r" ((value)));
    10191019
    10201020  return( swapped );
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