Ignore:
Timestamp:
Mar 24, 1998, 5:10:44 PM (23 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
bdac86b5
Parents:
d662fef8
Message:

Corrected register constraints per suggestion from Thomas Doerfler, IMD
<td@…>.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/powerpc/cpu.c

    rd662fef8 r72b397a  
    107107    unsigned32 tmp;
    108108
    109     asm volatile ("mfmsr %0" : "=r" (tmp));
     109    asm volatile ("mfmsr %0" : "=&r" (tmp));
    110110    msr = tmp;
    111111#ifdef ppc403
    112     asm volatile ("mfspr %0, 0x3d6" : "=r" (tmp)); /* EVPR */
     112    asm volatile ("mfspr %0, 0x3d6" : "=&r" (tmp)); /* EVPR */
    113113    evpr = tmp;
    114     asm volatile ("mfdcr %0, 0x42" : "=r" (tmp)); /* EXIER */
     114    asm volatile ("mfdcr %0, 0x42" : "=&r" (tmp)); /* EXIER */
    115115    exier = tmp;
    116116    asm volatile ("mtspr 0x3d6, %0" :: "r" (0)); /* EVPR */
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