Changeset 71af1a4 in rtems


Ignore:
Timestamp:
Jun 27, 2018, 10:17:21 AM (11 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
40f81ce6
Parents:
8f035cb
git-author:
Sebastian Huber <sebastian.huber@…> (06/27/18 10:17:21)
git-committer:
Sebastian Huber <sebastian.huber@…> (06/29/18 08:04:37)
Message:

riscv: Make some CPU port defines visible to asm

Move SREG and LREG assembler defines to <rtems/score/asm.h>.

Update #3433.

Location:
cpukit/score/cpu/riscv/include/rtems
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/riscv/include/rtems/asm.h

    r8f035cb r71af1a4  
    118118#define TYPE_FUNC(sym) .type SYM (sym), %function
    119119
     120#if __riscv_xlen == 32
     121
     122#define LREG lw
     123
     124#define SREG sw
     125
     126#elif __riscv_xlen == 64
     127
     128#define LREG ld
     129
     130#define SREG sd
     131
     132#endif /* __riscv_xlen */
     133
    120134.macro GET_SELF_CPU_CONTROL REG
    121135#ifdef RTEMS_SMP
  • cpukit/score/cpu/riscv/include/rtems/score/cpu.h

    r8f035cb r71af1a4  
    6565#define CPU_MODES_INTERRUPT_MASK   0x0000000000000001
    6666
     67#define CPU_CONTEXT_FP_SIZE  0
     68
     69#define CPU_PER_CPU_CONTROL_SIZE 0
     70
     71#define CPU_CACHE_LINE_BYTES 64
     72
     73#if __riscv_xlen == 32
     74
     75#define CPU_SIZEOF_POINTER 4
     76
     77#define CPU_STACK_MINIMUM_SIZE 4096
     78
     79#define CPU_EXCEPTION_FRAME_SIZE 128
     80
     81#elif __riscv_xlen == 64
     82
     83#define CPU_SIZEOF_POINTER 8
     84
     85#define CPU_STACK_MINIMUM_SIZE 8192
     86
     87#define CPU_EXCEPTION_FRAME_SIZE 256
     88
     89#endif /* __riscv_xlen */
     90
     91#define CPU_ALIGNMENT 8
     92
     93#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
     94
     95#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
     96
     97#define CPU_STACK_ALIGNMENT 16
     98
     99#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
     100
    67101/*
    68102 *  Processor defined structures required for cpukit/score.
     
    89123} Context_Control_fp;
    90124
    91 #define CPU_CONTEXT_FP_SIZE  0
    92125Context_Control_fp  _CPU_Null_fp_context;
    93126
    94 #define CPU_CACHE_LINE_BYTES 64
    95 
    96127#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
    97 #if __riscv_xlen == 32
    98 #define CPU_STACK_MINIMUM_SIZE  4096
    99 #else
    100 #define CPU_STACK_MINIMUM_SIZE  4096 * 2
    101 #endif
    102 #define CPU_ALIGNMENT 8
     128
    103129#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
    104 #define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
    105 #define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
    106 
    107 #define CPU_STACK_ALIGNMENT 16
    108 
    109 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
    110130
    111131#define _CPU_Initialize_vectors()
     
    231251  /* There is no CPU specific per-CPU state */
    232252} CPU_Per_CPU_control;
    233 #endif /* ASM */
    234 
    235 #if __riscv_xlen == 32
    236 #define CPU_SIZEOF_POINTER 4
    237 
    238 /* 32-bit load/store instructions */
    239 #define LREG lw
    240 #define SREG sw
    241 
    242 #define CPU_EXCEPTION_FRAME_SIZE 128
    243 #else /* xlen = 64 */
    244 #define CPU_SIZEOF_POINTER 8
    245 
    246 /* 64-bit load/store instructions */
    247 #define LREG ld
    248 #define SREG sd
    249 
    250 #define CPU_EXCEPTION_FRAME_SIZE 256
    251 #endif
    252 
    253 #define CPU_PER_CPU_CONTROL_SIZE 0
    254 
    255 #ifndef ASM
     253
    256254typedef uint16_t Priority_bit_map_Word;
    257255
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