Changeset 6ff3add in rtems


Ignore:
Timestamp:
May 27, 2009, 11:57:33 AM (10 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, master
Children:
64501892
Parents:
8ef7f20
Message:

2009-05-25 Allan Hessenflow <allanh@…>

PR 1418/bsps

  • mmu/mmu.c: enable mmu after initializing it.
  • mmu/mmu.h: add missing mmu flags entries.
  • include/mmuRegs.h: correct a couple field name typos.
Location:
c/src/lib/libcpu/bfin
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/bfin/ChangeLog

    r8ef7f20 r6ff3add  
     12009-05-25      Allan Hessenflow <allanh@kallisti.com>
     2
     3        * mmu/mmu.c: enable mmu after initializing it.
     4        * mmu/mmu.h: add missing mmu flags entries.
     5        * include/mmuRegs.h: correct a couple field name typos.
     6
    172008-09-25      Allan Hessenflow <allanh@kallisti.com>
    28
  • c/src/lib/libcpu/bfin/include/mmuRegs.h

    r8ef7f20 r6ff3add  
    5151#define ICPLB_DATA_CPLB_LRUPRIO                   0x00000100
    5252#define ICPLB_DATA_CPLB_USER_RD                   0x00000004
    53 #define ICPLB_DATA_CPLB_CPLB_LOCK                 0x00000002
    54 #define ICPLB_DATA_CPLB_CPLB_VALID                0x00000001
     53#define ICPLB_DATA_CPLB_LOCK                      0x00000002
     54#define ICPLB_DATA_CPLB_VALID                     0x00000001
    5555
    5656#endif /* _mmuRegs_h_ */
  • c/src/lib/libcpu/bfin/mmu/mmu.c

    r8ef7f20 r6ff3add  
    1414#include <rtems.h>
    1515
     16#include <libcpu/memoryRegs.h>
    1617#include "mmu.h"
    17 
    1818
    1919/* NOTE: see notes in mmu.h */
     
    3333    data += ICPLB_DATA_PITCH;
    3434  }
     35  *(uint32_t volatile *) IMEM_CONTROL |= IMEM_CONTROL_ENICPLB;
    3536  addr = (intptr_t) DCPLB_ADDR0;
    3637  data = (intptr_t) DCPLB_DATA0;
     
    4142    data += DCPLB_DATA_PITCH;
    4243  }
     44  *(uint32_t volatile *) DMEM_CONTROL |= DMEM_CONTROL_ENDCPLB;
    4345}
    4446
  • c/src/lib/libcpu/bfin/mmu/mmu.h

    r8ef7f20 r6ff3add  
    2626
    2727
     28#define INSTR_NOCACHE   (ICPLB_DATA_CPLB_USER_RD | \
     29                         ICPLB_DATA_CPLB_VALID)
     30
    2831#define INSTR_CACHEABLE (ICPLB_DATA_CPLB_L1_CHBL | \
    2932                         ICPLB_DATA_CPLB_USER_RD | \
    3033                         ICPLB_DATA_CPLB_VALID)
    3134
     35#define DATA_NOCACHE   (DCPLB_DATA_CPLB_DIRTY | \
     36                        DCPLB_DATA_CPLB_SUPV_WR | \
     37                        DCPLB_DATA_CPLB_USER_WR | \
     38                        DCPLB_DATA_CPLB_USER_RD | \
     39                        DCPLB_DATA_CPLB_VALID)
     40
    3241#define DATA_WRITEBACK (DCPLB_DATA_CPLB_L1_AOW | \
    3342                        DCPLB_DATA_CPLB_L1_CHBL | \
     43                        DCPLB_DATA_CPLB_DIRTY | \
    3444                        DCPLB_DATA_CPLB_SUPV_WR | \
    3545                        DCPLB_DATA_CPLB_USER_WR | \
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