Changeset 6f4e903 in rtems


Ignore:
Timestamp:
Sep 2, 2016, 11:30:20 PM (3 years ago)
Author:
Pavel Pisa <pisa@…>
Branches:
4.11
Children:
00dfdd6
Parents:
22cc8078
git-author:
Pavel Pisa <pisa@…> (09/02/16 23:30:20)
git-committer:
Pavel Pisa <pisa@…> (10/02/16 08:40:34)
Message:

bsps/arm: use defines for cache type register format field.

The change documents meaning of codes and opens
well defined way to use cache type format for cache
examination/debugging outside of arm-cp15.h file.

Updates #2782
Updates #2783

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/arm/shared/include/arm-cp15.h

    r22cc8078 r6f4e903  
    212212
    213213/**
     214 * @name CTR, Cache Type Register Defines
     215 *
     216 * The format can be obtained from CP15 by call
     217 * arm_cp15_cache_type_get_format(arm_cp15_get_cache_type());
     218 *
     219 * @{
     220 */
     221
     222#define ARM_CP15_CACHE_TYPE_FORMAT_ARMV6 0
     223#define ARM_CP15_CACHE_TYPE_FORMAT_ARMV7 4
     224
     225/** @} */
     226
     227/**
    214228 * @name CCSIDR, Cache Size ID Register Defines
    215229 *
     
    686700}
    687701
     702/* Extract format version from cache type CTR */
     703ARM_CP15_TEXT_SECTION static inline int
     704arm_cp15_cache_type_get_format(uint32_t ct)
     705{
     706  return (ct >> 29) & 0x7U;
     707}
     708
    688709/* Read size of smallest cache line of all instruction/data caches controlled by the processor */
    689710ARM_CP15_TEXT_SECTION static inline uint32_t
     
    692713  uint32_t mcls = 0;
    693714  uint32_t ct = arm_cp15_get_cache_type();
    694   uint32_t format = (ct >> 29) & 0x7U;
    695 
    696   if (format == 0x4) {
     715  uint32_t format = arm_cp15_cache_type_get_format(ct);
     716
     717  if (format == ARM_CP15_CACHE_TYPE_FORMAT_ARMV7) {
    697718    /* ARMv7 format */
    698719    mcls = (1U << (ct & 0xf)) * 4;
    699   } else if (format == 0x0) {
     720  } else if (format == ARM_CP15_CACHE_TYPE_FORMAT_ARMV6) {
    700721    /* ARMv6 format */
    701722    uint32_t mask = (1U << 12) - 1;
     
    715736  uint32_t mcls = 0;
    716737  uint32_t ct = arm_cp15_get_cache_type();
    717   uint32_t format = (ct >> 29) & 0x7U;
    718 
    719   if (format == 0x4) {
     738  uint32_t format = arm_cp15_cache_type_get_format(ct);
     739
     740  if (format == ARM_CP15_CACHE_TYPE_FORMAT_ARMV7) {
    720741    /* ARMv7 format */
    721742    mcls = (1U << ((ct & 0xf0000) >> 16)) * 4;
    722   } else if (format == 0x0) {
     743  } else if (format == ARM_CP15_CACHE_TYPE_FORMAT_ARMV6) {
    723744    /* ARMv6 format */
    724745    uint32_t mask = (1U << 12) - 1;
     
    735756  uint32_t mcls = 0;
    736757  uint32_t ct = arm_cp15_get_cache_type();
    737   uint32_t format = (ct >> 29) & 0x7U;
    738 
    739   if (format == 0x4) {
     758  uint32_t format = arm_cp15_cache_type_get_format(ct);
     759
     760  if (format == ARM_CP15_CACHE_TYPE_FORMAT_ARMV7) {
    740761    /* ARMv7 format */
    741762    mcls = (1U << (ct & 0x0000f)) * 4;
    742   } else if (format == 0x0) {
     763  } else if (format == ARM_CP15_CACHE_TYPE_FORMAT_ARMV6) {
    743764    /* ARMv6 format */
    744765    uint32_t mask = (1U << 12) - 1;
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