Changeset 6ec6ceb9 in rtems


Ignore:
Timestamp:
05/15/09 07:20:00 (13 years ago)
Author:
Thomas Doerfler <Thomas.Doerfler@…>
Branches:
4.10, 4.11, 5, master
Children:
3b7e9bc
Parents:
51dc1b3f
Message:

startup/bspstart.c: Fixed cache support functions. Enable FPU if the initialization tasks need them.

Location:
c/src/lib/libbsp/m68k/genmcf548x
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/m68k/genmcf548x/ChangeLog

    r51dc1b3f r6ec6ceb9  
     12009-05-11      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * startup/bspstart.c: Fixed cache support functions.  Enable FPU if the
     4        initialization tasks need them.
     5
    162009-04-28      Chris Johns <chrisj@rtems.org>
    27
  • c/src/lib/libbsp/m68k/genmcf548x/startup/bspstart.c

    r51dc1b3f r6ec6ceb9  
    6767 * CPU-space access
    6868 */
    69 #define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr))
    70 #define m68k_set_acr0(_acr0) asm volatile ("movec %0,#0x0004" : : "d" (_acr0))
    71 #define m68k_set_acr1(_acr1) asm volatile ("movec %0,#0x0005" : : "d" (_acr1))
    7269#define m68k_set_acr2(_acr2) asm volatile ("movec %0,#0x0005" : : "d" (_acr2))
    7370#define m68k_set_acr3(_acr3) asm volatile ("movec %0,#0x0007" : : "d" (_acr3))
    7471
    7572/*
    76  * Set initial cacr mode, mainly enables branch/intruction/data cache and switch off FPU.
    77  */
    78 static uint32_t cacr_mode = (0                                          |
    79                              MCF548X_CACR_DEC                           | /* enable data cache */
    80                              MCF548X_CACR_BEC                           | /* enable branch cache */
    81                              MCF548X_CACR_IEC                           | /* enable instruction cache */
    82                              MCF548X_CACR_DDCM(DCACHE_ON_WRIGHTTHROUGH) | /* set data cache mode to write-through */
    83                              MCF548X_CACR_DESB                          | /* enable data store buffer */
    84                              MCF548X_CACR_DDSP                          | /* data access only in supv. mode */
    85                              MCF548X_CACR_IDSP                          | /* instr. access only in supv. mode */
    86                              MCF548X_CACR_DF);                            /* disable FPU */
    87 
    88 
    89 /*
    90  * Coldfire cacr maintenance functions
    91  */
    92 void _CPU_cacr_set_mode(uint32_t new_cacr_mode)
    93 {
    94 rtems_interrupt_level level;
    95 
    96 rtems_interrupt_disable(level);
    97 cacr_mode = new_cacr_mode;
    98 m68k_set_cacr(new_cacr_mode);
    99 rtems_interrupt_enable(level);
     73 * Set initial cacr mode, mainly enables branch/intruction/data cache and
     74 * switch off FPU.
     75 */
     76static const uint32_t BSP_CACR_INIT = MCF548X_CACR_DEC /* enable data cache */
     77  | MCF548X_CACR_BEC /* enable branch cache */
     78  | MCF548X_CACR_IEC /* enable instruction cache */
     79  | MCF548X_CACR_DDCM(DCACHE_ON_WRIGHTTHROUGH)
     80      /* set data cache mode to write-through */
     81  | MCF548X_CACR_DESB /* enable data store buffer */
     82  | MCF548X_CACR_DDSP /* data access only in supv. mode */
     83  | MCF548X_CACR_IDSP /* instr. access only in supv. mode */
     84  | MCF548X_CACR_DF; /* disable FPU */
     85
     86/*
     87 * CACR maintenance functions
     88 */
     89
     90void bsp_cacr_set_flags( uint32_t flags)
     91{
     92  rtems_interrupt_level level;
     93
     94  rtems_interrupt_disable( level);
     95  _CPU_cacr_shadow |= flags;
     96  m68k_set_cacr( _CPU_cacr_shadow);
     97  rtems_interrupt_enable( level);
     98}
     99
     100void bsp_cacr_set_self_clear_flags( uint32_t flags)
     101{
     102  rtems_interrupt_level level;
     103  uint32_t cacr = 0;
     104
     105  rtems_interrupt_disable( level);
     106  cacr = _CPU_cacr_shadow | flags;
     107  m68k_set_cacr( cacr);
     108  rtems_interrupt_enable( level);
     109}
     110
     111void bsp_cacr_clear_flags( uint32_t flags)
     112{
     113  rtems_interrupt_level level;
     114
     115  rtems_interrupt_disable( level);
     116  _CPU_cacr_shadow &= ~flags;
     117  m68k_set_cacr( _CPU_cacr_shadow);
     118  rtems_interrupt_enable( level);
    100119}
    101120
     
    105124void _CPU_cache_freeze_data(void)
    106125{
     126  /* Do nothing */
    107127}
    108128
    109129void _CPU_cache_unfreeze_data(void)
    110130{
     131  /* Do nothing */
    111132}
    112133
    113134void _CPU_cache_freeze_instruction(void)
    114135{
     136  /* Do nothing */
    115137}
    116138
    117139void _CPU_cache_unfreeze_instruction(void)
    118140{
     141  /* Do nothing */
    119142}
    120143
    121144void _CPU_cache_enable_instruction(void)
    122145{
    123     cacr_mode &= ~(MCF548X_CACR_IDCM);
    124     _CPU_cacr_set_mode(cacr_mode);
     146  bsp_cacr_clear_flags( MCF548X_CACR_IDCM);
    125147}
    126148
    127149void _CPU_cache_disable_instruction(void)
    128150{
    129     cacr_mode |= MCF548X_CACR_IDCM;
    130     _CPU_cacr_set_mode(cacr_mode);
     151  bsp_cacr_set_flags( MCF548X_CACR_IDCM);
    131152}
    132153
    133154void _CPU_cache_invalidate_entire_instruction(void)
    134155{
    135         cacr_mode |= MCF548X_CACR_ICINVA;
    136     _CPU_cacr_set_mode(cacr_mode);
     156  bsp_cacr_set_self_clear_flags( MCF548X_CACR_ICINVA);
    137157}
    138158
    139159void _CPU_cache_invalidate_1_instruction_line(const void *addr)
    140160{
    141 
    142     asm volatile ("cpushl %%ic,(%0)" :: "a" (addr));
     161  uint32_t a = (uint32_t) addr & ~0x3;
     162
     163  asm volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x0));
     164  asm volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x1));
     165  asm volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x2));
     166  asm volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x3));
    143167}
    144168
    145169void _CPU_cache_enable_data(void)
    146170{
    147     cacr_mode &= ~MCF548X_CACR_DDCM(DCACHE_OFF_IMPRECISE);
    148     _CPU_cacr_set_mode(cacr_mode);
     171  bsp_cacr_clear_flags( MCF548X_CACR_DDCM( DCACHE_OFF_IMPRECISE));
    149172}
    150173
    151174void _CPU_cache_disable_data(void)
    152175{
    153     cacr_mode |= MCF548X_CACR_DDCM(DCACHE_OFF_IMPRECISE);
    154     _CPU_cacr_set_mode(cacr_mode);
     176  bsp_cacr_set_flags( MCF548X_CACR_DDCM( DCACHE_OFF_IMPRECISE));
    155177}
    156178
    157179void _CPU_cache_invalidate_entire_data(void)
    158180{
    159     cacr_mode |= MCF548X_CACR_DCINVA;
    160     _CPU_cacr_set_mode(cacr_mode);
    161 }
    162 
    163 void _CPU_cache_invalidate_1_data_line(const void *addr)
    164 {
    165 
    166    asm volatile ("cpushl %%dc,(%0)" :: "a" (addr));
    167 }
    168 
    169 void _CPU_cache_flush_1_data_line(const void *addr)
    170 {
    171    asm volatile ("cpushl %%dc,(%0)" :: "a" (addr));
    172 }
    173 
    174 void _CPU_cache_flush_entire_data(void)
    175 {
    176 register uint32_t way_cnt, set_cnt, addr;
    177 
    178 asm volatile("nop");
    179 
    180 for(way_cnt=0; way_cnt<4; way_cnt++)
    181   {
    182   for(addr=0,set_cnt=0; set_cnt<512; set_cnt++,addr+=0x10)
    183     {
    184     asm volatile ("cpushl %%dc,(%0)" :: "a" (addr));
    185     }
    186   addr=way_cnt;
     181  bsp_cacr_set_self_clear_flags( MCF548X_CACR_DCINVA);
     182}
     183
     184void _CPU_cache_invalidate_1_data_line( const void *addr)
     185{
     186  uint32_t a = (uint32_t) addr & ~0x3;
     187
     188  asm volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x0));
     189  asm volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x1));
     190  asm volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x2));
     191  asm volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x3));
     192}
     193
     194void _CPU_cache_flush_1_data_line( const void *addr)
     195{
     196  uint32_t a = (uint32_t) addr & ~0x3;
     197
     198  asm volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x0));
     199  asm volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x1));
     200  asm volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x2));
     201  asm volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x3));
     202}
     203
     204void _CPU_cache_flush_entire_data( void)
     205{
     206  uint32_t line = 0;
     207
     208  for (line = 0; line < 512; ++line) {
     209    _CPU_cache_flush_1_data_line( (const void *) (line * 16));
    187210  }
    188211}
     
    248271void bsp_start( void )
    249272{
     273  /* Initialize CACR shadow register */
     274  _CPU_cacr_shadow = BSP_CACR_INIT;
     275
     276  /* Switch on FPU in CACR shadow register if necessary */
     277  if (
     278    Configuration_RTEMS_API.User_initialization_tasks_table != NULL &&
     279      (Configuration_RTEMS_API.User_initialization_tasks_table->attribute_set
     280        & RTEMS_FLOATING_POINT) != 0
     281  ) {
     282    _CPU_cacr_shadow &= ~MCF548X_CACR_DF;
     283  }
     284
     285  /*
     286   * Load the shadow variable of CACR with initial mode and write it to the
     287   * CACR.  Interrupts are still disabled, so there is no need for surrounding
     288   * rtems_interrupt_enable() / rtems_interrupt_disable().
     289   */
     290  m68k_set_cacr( _CPU_cacr_shadow);
     291
    250292  /*
    251293   * do mapping of acr's and/or mmu
    252294   */
    253295  acr_mmu_mapping();
    254 
    255   /*
    256    * Load the shadow variable of cacr with initial mode and write it to the cacr.
    257    * Interrupts are still disabled, so there is no need for surrounding rtems_interrupt_enable()/rtems_interrupt_disable()
    258    */
    259   _CPU_cacr_shadow = cacr_mode;
    260   m68k_set_cacr(_CPU_cacr_shadow);
    261 
    262296}
    263297
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