Changeset 6e6815e in umon for main/cpu/arm/arm.h


Ignore:
Timestamp:
Jun 20, 2016, 3:24:20 PM (3 years ago)
Author:
Ben Gras <beng@…>
Branches:
master
Parents:
696ee75
git-author:
Ben Gras <beng@…> (06/20/16 15:24:20)
git-committer:
Ben Gras <beng@…> (06/20/16 15:45:45)
Message:

ARM: save and print exception context

Debugging aid. Prints nice exception context info like:

R0 = 0x00000000 R8 = 0x402fe8b0
R1 = 0x402ffd80 R9 = 0x40309b15
R2 = 0x00000800 R10 = 0x00000000
R3 = 0x402ffd40 R11 = 0x00000000
R4 = 0x402ffd40 R12 = 0x402fdd38
R5 = 0x402ffd80 SP = 0x40309694
R6 = 0x00000003 LR = 0x402fa348
R7 = 0x00000800 PC = 0x402f8614
VEC = 0x00000003

Data structures, definitions and code taken from RTEMS.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • main/cpu/arm/arm.h

    r696ee75 r6e6815e  
    7777#define VEC_RESERVED         6
    7878#define VEC_FIQ              7
     79
     80/* Taken from RTEMS score/cpu.h */
     81#define ARM_EXCEPTION_FRAME_SIZE 80
     82#define ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET 52
     83#define ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET 72
     84
     85#define ARM_PSR_N (1 << 31)
     86#define ARM_PSR_Z (1 << 30)
     87#define ARM_PSR_C (1 << 29)
     88#define ARM_PSR_V (1 << 28)
     89#define ARM_PSR_Q (1 << 27)
     90#define ARM_PSR_J (1 << 24)
     91#define ARM_PSR_GE_SHIFT 16
     92#define ARM_PSR_GE_MASK (0xf << ARM_PSR_GE_SHIFT)
     93#define ARM_PSR_E (1 << 9)
     94#define ARM_PSR_A (1 << 8)
     95#define ARM_PSR_I (1 << 7)
     96#define ARM_PSR_F (1 << 6)
     97#define ARM_PSR_T (1 << 5)
     98#define ARM_PSR_M_SHIFT 0
     99#define ARM_PSR_M_MASK (0x1f << ARM_PSR_M_SHIFT)
     100#define ARM_PSR_M_USR 0x10
     101#define ARM_PSR_M_FIQ 0x11
     102#define ARM_PSR_M_IRQ 0x12
     103#define ARM_PSR_M_SVC 0x13
     104#define ARM_PSR_M_ABT 0x17
     105#define ARM_PSR_M_UND 0x1b
     106#define ARM_PSR_M_SYS 0x1f
     107
     108#ifndef _ASSEMBLY_
     109
     110#include "stddefs.h"
     111
     112/* Exception context.
     113 * These data structures gratefully taken from the RTEMS
     114 * source code cpukit/score/cpu/arm/rtems/score/cpu.h
     115 */
     116
     117typedef struct {
     118  uint32_t register_fpexc;
     119  uint32_t register_fpscr;
     120  uint64_t register_d0;
     121  uint64_t register_d1;
     122  uint64_t register_d2;
     123  uint64_t register_d3;
     124  uint64_t register_d4;
     125  uint64_t register_d5;
     126  uint64_t register_d6;
     127  uint64_t register_d7;
     128  uint64_t register_d8;
     129  uint64_t register_d9;
     130  uint64_t register_d10;
     131  uint64_t register_d11;
     132  uint64_t register_d12;
     133  uint64_t register_d13;
     134  uint64_t register_d14;
     135  uint64_t register_d15;
     136  uint64_t register_d16;
     137  uint64_t register_d17;
     138  uint64_t register_d18;
     139  uint64_t register_d19;
     140  uint64_t register_d20;
     141  uint64_t register_d21;
     142  uint64_t register_d22;
     143  uint64_t register_d23;
     144  uint64_t register_d24;
     145  uint64_t register_d25;
     146  uint64_t register_d26;
     147  uint64_t register_d27;
     148  uint64_t register_d28;
     149  uint64_t register_d29;
     150  uint64_t register_d30;
     151  uint64_t register_d31;
     152} ARM_VFP_context;
     153
     154typedef struct {
     155  uint32_t register_r0;
     156  uint32_t register_r1;
     157  uint32_t register_r2;
     158  uint32_t register_r3;
     159  uint32_t register_r4;
     160  uint32_t register_r5;
     161  uint32_t register_r6;
     162  uint32_t register_r7;
     163  uint32_t register_r8;
     164  uint32_t register_r9;
     165  uint32_t register_r10;
     166  uint32_t register_r11;
     167  uint32_t register_r12;
     168  uint32_t register_sp;
     169  void *register_lr;
     170  void *register_pc;
     171  uint32_t register_cpsr;
     172  int vector;
     173  const ARM_VFP_context *vfp_context;
     174  uint32_t reserved_for_stack_alignment;
     175} CPU_Exception_frame;
     176
     177#endif
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