Changeset 6c68186 in rtems


Ignore:
Timestamp:
Oct 12, 2000, 12:50:43 PM (20 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
50bb7627
Parents:
b0005bb1
Message:

2000-10-12 John S Gwynne <jgwynne@…>

  • sim.h: These changes enable RTEMS to automatically generate the ram_init file used by gdb with the BDM patches. The 332 has on-board chip select lines (for RAM and FLASH) that must be configured before use of these peripherals. These patches parse data from start.c where the chip select lines are configured in the runtime executable and automatically generates the gdb initialization file using the same settings. A great time saver. A similar file, ram_init_FW (flash writable), is also generated that the flash programming tool uses.
  • BSP/start/start.c: Must be modified to support above.
  • BSP/start/ram_init.ld, BSP/start/ram_init.sed: New files.
Files:
5 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/m68k/ChangeLog

    rb0005bb1 r6c68186  
     12000-10-12      John S Gwynne <jgwynne@mrcday.com>
     2
     3        * sim.h: These changes enable RTEMS to automatically generate
     4        the ram_init file used by gdb with the BDM patches. The 332 has
     5        on-board chip select lines (for RAM and FLASH) that must be
     6        configured before use of these peripherals. These patches parse
     7        data from start.c where the chip select lines are configured in
     8        the runtime executable and automatically generates the gdb
     9        initialization file using the same settings. A great time saver.
     10        A similar file, ram_init_FW (flash writable), is also generated
     11        that the flash programming tool uses.
     12        * BSP/start/start.c: Must be modified to support above.
     13        * BSP/start/ram_init.ld, BSP/start/ram_init.sed: New files.
     14
    1152000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    216
  • c/src/exec/score/cpu/m68k/sim.h

    rb0005bb1 r6c68186  
    6969/* SIM_CRB (SIM Control Register Block) base address of the SIM
    7070   control registers */
    71 /* not included in ram_init.h */
     71#ifndef SIM_CRB
    7272#if SIM_MM == 0
    7373#define SIM_CRB 0x7ffa00
    74 #else
     74#else /* SIM_MM */
    7575#undef SIM_MM
    7676#define SIM_MM 1
    7777#define SIM_CRB 0xfffa00
    78 #endif
    79 /* end not included in ram_init.h */
    80 
     78#endif /* SIM_MM */
     79#endif /* SIM_CRB */
    8180
    8281
  • cpukit/score/cpu/m68k/ChangeLog

    rb0005bb1 r6c68186  
     12000-10-12      John S Gwynne <jgwynne@mrcday.com>
     2
     3        * sim.h: These changes enable RTEMS to automatically generate
     4        the ram_init file used by gdb with the BDM patches. The 332 has
     5        on-board chip select lines (for RAM and FLASH) that must be
     6        configured before use of these peripherals. These patches parse
     7        data from start.c where the chip select lines are configured in
     8        the runtime executable and automatically generates the gdb
     9        initialization file using the same settings. A great time saver.
     10        A similar file, ram_init_FW (flash writable), is also generated
     11        that the flash programming tool uses.
     12        * BSP/start/start.c: Must be modified to support above.
     13        * BSP/start/ram_init.ld, BSP/start/ram_init.sed: New files.
     14
    1152000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    216
  • cpukit/score/cpu/m68k/rtems/m68k/sim.h

    rb0005bb1 r6c68186  
    6969/* SIM_CRB (SIM Control Register Block) base address of the SIM
    7070   control registers */
    71 /* not included in ram_init.h */
     71#ifndef SIM_CRB
    7272#if SIM_MM == 0
    7373#define SIM_CRB 0x7ffa00
    74 #else
     74#else /* SIM_MM */
    7575#undef SIM_MM
    7676#define SIM_MM 1
    7777#define SIM_CRB 0xfffa00
    78 #endif
    79 /* end not included in ram_init.h */
    80 
     78#endif /* SIM_MM */
     79#endif /* SIM_CRB */
    8180
    8281
  • cpukit/score/cpu/m68k/sim.h

    rb0005bb1 r6c68186  
    6969/* SIM_CRB (SIM Control Register Block) base address of the SIM
    7070   control registers */
    71 /* not included in ram_init.h */
     71#ifndef SIM_CRB
    7272#if SIM_MM == 0
    7373#define SIM_CRB 0x7ffa00
    74 #else
     74#else /* SIM_MM */
    7575#undef SIM_MM
    7676#define SIM_MM 1
    7777#define SIM_CRB 0xfffa00
    78 #endif
    79 /* end not included in ram_init.h */
    80 
     78#endif /* SIM_MM */
     79#endif /* SIM_CRB */
    8180
    8281
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