Index: c/src/lib/libbsp/arm/xilinx-zynq/include/bsp.h
===================================================================
--- c/src/lib/libbsp/arm/xilinx-zynq/include/bsp.h	(revision 4a9e52eefc510d7022ddc61c4ecde8db6b9a0217)
+++ c/src/lib/libbsp/arm/xilinx-zynq/include/bsp.h	(revision 6c1e53014ec551d2702e3d2dae11e548e12412c2)
@@ -27,4 +27,5 @@
 
 #include <bsp/default-initial-extension.h>
+#include <bsp/start.h>
 
 #ifdef __cplusplus
@@ -47,4 +48,12 @@
 void zynq_fatal(zynq_fatal_code code) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
 
+/*
+ * Zynq specific set up of the MMU. Provide in the application to override
+ * the defaults in the BSP. Note the defaults do not map in the GP0 and GP1
+ * AXI ports. You should add the specific regions that map into your
+ * PL rather than just open the whole of the GP[01] address space up.
+ */
+BSP_START_TEXT_SECTION void zynq_setup_mmu_and_cache(void);
+
 #ifdef __cplusplus
 }
Index: c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c
===================================================================
--- c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c	(revision 4a9e52eefc510d7022ddc61c4ecde8db6b9a0217)
+++ c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c	(revision 6c1e53014ec551d2702e3d2dae11e548e12412c2)
@@ -18,34 +18,4 @@
 #include <bsp/arm-a9mpcore-start.h>
 
-BSP_START_DATA_SECTION static const arm_cp15_start_section_config
-zynq_mmu_config_table[] = {
-  ARMV7_CP15_START_DEFAULT_SECTIONS,
-  {
-    .begin = 0xe0000000U,
-    .end = 0xe0200000U,
-    .flags = ARMV7_MMU_DEVICE
-  }, {
-    .begin = 0xf8000000U,
-    .end = 0xf9000000U,
-    .flags = ARMV7_MMU_DEVICE
-  }
-};
-
-BSP_START_TEXT_SECTION static void setup_mmu_and_cache(void)
-{
-  uint32_t ctrl = arm_cp15_start_setup_mmu_and_cache(
-    ARM_CP15_CTRL_A,
-    ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z
-  );
-
-  arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache(
-    ctrl,
-    (uint32_t *) bsp_translation_table_base,
-    ARM_MMU_DEFAULT_CLIENT_DOMAIN,
-    &zynq_mmu_config_table[0],
-    RTEMS_ARRAY_SIZE(zynq_mmu_config_table)
-  );
-}
-
 BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
 {
@@ -57,5 +27,5 @@
   arm_a9mpcore_start_hook_1();
   bsp_start_copy_sections();
-  setup_mmu_and_cache();
+  zynq_setup_mmu_and_cache();
   bsp_start_clear_bss();
 }
Index: c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstartmmu.c
===================================================================
--- c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstartmmu.c	(revision 6c1e53014ec551d2702e3d2dae11e548e12412c2)
+++ c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstartmmu.c	(revision 6c1e53014ec551d2702e3d2dae11e548e12412c2)
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <bsp.h>
+#include <bsp/start.h>
+#include <bsp/arm-cp15-start.h>
+#include <bsp/arm-a9mpcore-start.h>
+
+BSP_START_DATA_SECTION static const arm_cp15_start_section_config
+zynq_mmu_config_table[] = {
+  ARMV7_CP15_START_DEFAULT_SECTIONS,
+  {
+    .begin = 0xe0000000U,
+    .end = 0xe0200000U,
+    .flags = ARMV7_MMU_DEVICE
+  }, {
+    .begin = 0xf8000000U,
+    .end = 0xf9000000U,
+    .flags = ARMV7_MMU_DEVICE
+  }
+};
+
+/*
+ * Make weak and let the user override.
+ */
+BSP_START_TEXT_SECTION void zynq_setup_mmu_and_cache(void) __attribute__ ((weak));
+
+BSP_START_TEXT_SECTION void zynq_setup_mmu_and_cache(void)
+{
+  uint32_t ctrl = arm_cp15_start_setup_mmu_and_cache(
+    ARM_CP15_CTRL_A,
+    ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z
+  );
+
+  arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache(
+    ctrl,
+    (uint32_t *) bsp_translation_table_base,
+    ARM_MMU_DEFAULT_CLIENT_DOMAIN,
+    &zynq_mmu_config_table[0],
+    RTEMS_ARRAY_SIZE(zynq_mmu_config_table)
+  );
+}
