Changeset 6c1e530 in rtems


Ignore:
Timestamp:
Dec 19, 2013, 3:44:29 AM (5 years ago)
Author:
Chris Johns <chrisj@…>
Branches:
4.11, master
Children:
f466e56
Parents:
4a9e52e
Message:

arm/zynq: Add support for application supplied MMU tables.

Users can provide a zynq_setup_mmu_and_cache function that sets
up the MMU. The Zynq's PL logic means users can vary the MMU.

Location:
c/src/lib/libbsp/arm/xilinx-zynq
Files:
1 added
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/xilinx-zynq/include/bsp.h

    r4a9e52e r6c1e530  
    2727
    2828#include <bsp/default-initial-extension.h>
     29#include <bsp/start.h>
    2930
    3031#ifdef __cplusplus
     
    4748void zynq_fatal(zynq_fatal_code code) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
    4849
     50/*
     51 * Zynq specific set up of the MMU. Provide in the application to override
     52 * the defaults in the BSP. Note the defaults do not map in the GP0 and GP1
     53 * AXI ports. You should add the specific regions that map into your
     54 * PL rather than just open the whole of the GP[01] address space up.
     55 */
     56BSP_START_TEXT_SECTION void zynq_setup_mmu_and_cache(void);
     57
    4958#ifdef __cplusplus
    5059}
  • c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c

    r4a9e52e r6c1e530  
    1818#include <bsp/arm-a9mpcore-start.h>
    1919
    20 BSP_START_DATA_SECTION static const arm_cp15_start_section_config
    21 zynq_mmu_config_table[] = {
    22   ARMV7_CP15_START_DEFAULT_SECTIONS,
    23   {
    24     .begin = 0xe0000000U,
    25     .end = 0xe0200000U,
    26     .flags = ARMV7_MMU_DEVICE
    27   }, {
    28     .begin = 0xf8000000U,
    29     .end = 0xf9000000U,
    30     .flags = ARMV7_MMU_DEVICE
    31   }
    32 };
    33 
    34 BSP_START_TEXT_SECTION static void setup_mmu_and_cache(void)
    35 {
    36   uint32_t ctrl = arm_cp15_start_setup_mmu_and_cache(
    37     ARM_CP15_CTRL_A,
    38     ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z
    39   );
    40 
    41   arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache(
    42     ctrl,
    43     (uint32_t *) bsp_translation_table_base,
    44     ARM_MMU_DEFAULT_CLIENT_DOMAIN,
    45     &zynq_mmu_config_table[0],
    46     RTEMS_ARRAY_SIZE(zynq_mmu_config_table)
    47   );
    48 }
    49 
    5020BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
    5121{
     
    5727  arm_a9mpcore_start_hook_1();
    5828  bsp_start_copy_sections();
    59   setup_mmu_and_cache();
     29  zynq_setup_mmu_and_cache();
    6030  bsp_start_clear_bss();
    6131}
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