Changeset 69effbb4 in rtems


Ignore:
Timestamp:
Jul 11, 2008, 10:00:41 AM (11 years ago)
Author:
Thomas Doerfler <Thomas.Doerfler@…>
Branches:
4.10, 4.11, 4.9, master
Children:
a86f3aac
Parents:
1898d72
Message:

added variant to gen68360 BSP
added genmcf548x BSP

Location:
c/src/lib/libbsp/m68k
Files:
24 added
7 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/m68k/ChangeLog

    r1898d72 r69effbb4  
     12008-07-11      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
     2
     3        * genmcf548x: added BSP
     4
    152008-06-27      Joel Sherrill <joel.sherrill@OARcorp.com>
    26
  • c/src/lib/libbsp/m68k/acinclude.m4

    r1898d72 r69effbb4  
    1313  gen68360 )
    1414    AC_CONFIG_SUBDIRS([gen68360]);;
     15  genmcf548x )
     16    AC_CONFIG_SUBDIRS([genmcf548x]);;
    1517  idp )
    1618    AC_CONFIG_SUBDIRS([idp]);;
  • c/src/lib/libbsp/m68k/gen68360/ChangeLog

    r1898d72 r69effbb4  
     12008-07-09      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
     2
     3        * Makefile.am, spi/m360_spidrv.c, spi/m360_spidrv.h:
     4        added SPI driver
     5
     62008-07-09      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
     7
     8        * README:
     9        added pgh360 BSP variant
     10
    1112008-05-23      Joel Sherrill <joel.sherrill@OARcorp.com>
    212
  • c/src/lib/libbsp/m68k/gen68360/Makefile.am

    r1898d72 r69effbb4  
    1212include_HEADERS = include/bsp.h
    1313include_HEADERS += include/tm27.h
    14 
    1514nodist_include_HEADERS = include/bspopts.h
    1615DISTCLEANFILES = include/bspopts.h
  • c/src/lib/libbsp/m68k/gen68360/README

    r1898d72 r69effbb4  
    3030#       - If the preprocessor symbol M68360_ATLAS_HSB is defined,
    3131#         the BSP is compiled for an Atlas HSB card.
     32#       - If the preprocessor symbol M68360_IMD_PGH is defined,
     33#         the BSP is compiled for an IMD PGH360 card.
    3234#       - Otherwise, the BSP is compiled for a generic 68360 system
    3335#         as described in Chapter 9 of the MC68360 User's Manual.  This
     
    4042BOARD:              Atlas Computer Equipment Inc. Advanced Communication Engine (ACE)
    4143BOARD:              Arnewsh SBC360 68040/68360 card
     44BOARD:              IMD PGH Board (custom)
    4245BUS:                none
    4346CPU FAMILY:         Motorola CPU32+, Motorola 68040
     
    8386ROM:            To 1 MByte, 180 nsec (3 wait states), chip select 0
    8487RAM:            4 or 16 MBytes of 60 nsec parity DRAM (1Mx36) to RAS1*/CAS1*
     88
     89Board description (IMD PGH)
     90---------------------------
     91clock rate:     25 MHz
     92bus width:      8-bit PROM/FLASH, 32-bit DRAM
     93ROM:            512KByte, 180 nsec (3 wait states), chip select 0
     94RAM:            16 MBytes of 60 nsec no-parity DRAM (1Mx32) to RAS1*/CAS1*
    8595
    8696Host System
     
    293303                P.O. Box 270352
    294304                Fort Collins, CO 80527-0352
     305        A custom 68360 board (PGH360) produced by IMD
  • c/src/lib/libbsp/m68k/gen68360/include/bsp.h

    r1898d72 r69effbb4  
    9191extern char M360DefaultWatchdogFeeder;
    9292
     93extern int m360_clock_rate; /* BRG clock rate, defined in console.c */
     94
    9395m68k_isr_entry set_vector(
    9496  rtems_isr_entry     handler,
     
    103105extern char _HeapSize[];
    104106
     107
    105108/*
    106109 * Definitions for Atlas Computer Equipment Inc. High Speed Bridge (HSB)
     
    112115#define ATLASHSB_ROM_U6 0xFF080000L     /* U6 flash ROM socket */
    113116
     117
     118  /*
     119   * definitions for PGH360 board
     120   */
     121#if defined(PGH360)
     122/*
     123 * logical SPI addresses of SPI slaves available
     124 */
     125#define PGH360_SPI_ADDR_EEPROM     0
     126#define PGH360_SPI_ADDR_DISP4_DATA 1
     127#define PGH360_SPI_ADDR_DISP4_CTRL 2
     128
     129/*
     130 * Port B bit locations of SPI slave selects
     131 */
     132#define PGH360_PB_SPI_DISP4_RS_MSK   (1<<15)
     133#define PGH360_PB_SPI_DISP4_CE_MSK   (1<<14)
     134#define PGH360_PB_SPI_EEP_CE_MSK     (1<< 0)
     135#endif /* defined(PGH360) */
     136
    114137#ifdef __cplusplus
    115138}
  • c/src/lib/libbsp/m68k/gen68360/startup/init68360.c

    r1898d72 r69effbb4  
    1414#include <bsp.h>
    1515#include <rtems/m68k/m68360.h>
     16
     17
     18/*
     19 * Declare the m360 structure here for the benefit of the debugger
     20 */
     21
     22volatile m360_t m360;
    1623
    1724/*
     
    335342         *      BCLRO* arbitration level 3
    336343         */
     344
     345#elif defined(PGH360)
     346        /*
     347         * Step 6: Is this a power-up reset?
     348         * For now we just ignore this and do *all* the steps
     349         * Someday we might want to:
     350         *      if (Hard, Loss of Clock, Power-up)
     351         *              Do all steps
     352         *      else if (Double bus fault, watchdog or soft reset)
     353         *              Skip to step 12
     354         *      else (must be a CPU32+ reset command)
     355         *              Skip to step 14
     356         */
     357
     358        /*
     359         * Step 7: Deal with clock synthesizer
     360         * HARDWARE:
     361         *      Change if you're not using an external 25 MHz oscillator.
     362         */
     363        m360.clkocr = 0x8e;     /* No more writes, CLKO1=1/3, CLKO2=off */
     364        /*
     365         * adjust crystal to average between 4.19 MHz and 4.00 MHz
     366         * reprogram pll
     367         */
     368        m360.pllcr = 0xA000+(24576000/((4000000+4194304)/2/128))-1;
     369                                        /* LPSTOP slowdown, PLL /128*??? */
     370        m360.cdvcr = 0x8000;    /* No more writes, no clock division */
     371
     372        /*
     373         * Step 8: Initialize system protection
     374         *      Enable watchdog
     375         *      Watchdog causes system reset
     376         *      128 sec. watchdog timeout
     377         *      Enable double bus fault monitor
     378         *      Enable bus monitor external
     379         *      128 clocks for external timeout
     380         */
     381        m360.sypcr = 0xEF;
     382        /*
     383         * also initialize the SWP bit in PITR to 1
     384         */
     385        m360.pitr |= 0x0200;
     386        /*
     387         * and trigger SWSR twice to ensure, that interval starts right now
     388         */
     389        m360.swsr = 0x55;
     390        m360.swsr = 0xAA;
     391        m360.swsr = 0x55;
     392        m360.swsr = 0xAA;
     393        /*
     394         * Step 9: Clear parameter RAM and reset communication processor module
     395         */
     396        for (i = 0 ; i < 192  ; i += sizeof (long)) {
     397                *((long *)((char *)&m360 + 0xC00 + i)) = 0;
     398                *((long *)((char *)&m360 + 0xD00 + i)) = 0;
     399                *((long *)((char *)&m360 + 0xE00 + i)) = 0;
     400                *((long *)((char *)&m360 + 0xF00 + i)) = 0;
     401        }
     402        M360ExecuteRISC (M360_CR_RST);
     403
     404        /*
     405         * Step 10: Write PEPAR
     406         *      SINTOUT not used (CPU32+ mode)
     407         *      CF1MODE=00 (CONFIG1 input)
     408         *      IPIPE1
     409         *      WE0-3
     410         *      OE* output
     411         *      CAS2* / CAS3*
     412         *      CAS0* / CAS1*
     413         *      CS7*
     414         *      AVEC*
     415         * HARDWARE:
     416         *      Change if you are using a different memory configuration
     417         *      (static RAM, external address multiplexing, etc).
     418         */
     419        m360.pepar = 0x0080;
     420        /*
     421         * Step 11: Remap Chip Select 0 (CS0*), set up GMR
     422         *      no DRAM support
     423         * HARDWARE:
     424         *      Change if you are using a different memory configuration
     425         */
     426        m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN      | M360_GMR_RCYC(0) |
     427                   M360_GMR_PGS(6)   | M360_GMR_DPS_32BIT | M360_GMR_DWQ     |
     428                   M360_GMR_GAMX;
     429
     430        m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
     431                                                        M360_MEMC_BR_V;
     432        m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_512KB |
     433                                                        M360_MEMC_OR_8BIT;
     434
     435        /*
     436         * Step 12: Initialize the system RAM
     437         *      Set up option/base registers
     438         *              16 MB DRAM
     439         *              1 wait state
     440         * HARDWARE:
     441         *      Change if you are using a different memory configuration
     442         *      NOTE: no Page mode possible for EDO RAMs (?)
     443         */
     444        ramSize = 16 * 1024 * 1024;
     445        m360.memc[7].or = M360_MEMC_OR_TCYC(1)  | M360_MEMC_OR_16MB |
     446                          M360_MEMC_OR_FCMC(0)  | /* M360_MEMC_OR_PGME | */
     447                          M360_MEMC_OR_32BIT    | M360_MEMC_OR_DRAM;
     448        m360.memc[7].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
     449
     450        /*
     451         * FIXME: here we should wait for 8 refresh cycles...
     452         */
     453        /*
     454         * Step 12a: test the ram, if wanted
     455         * FIXME: when do we call this?
     456         * -> only during firmware execution
     457         * -> perform intesive test only on request
     458         * -> ensure, that results are stored properly
     459         */
     460#if 0 /* FIXME: activate RAM tests again */
     461        {
     462          void *ram_base, *ram_end, *code_loc;
     463          extern char ramtest_start,ramtest_end;
     464          ram_base = &ramtest_start;
     465          ram_end  = &ramtest_end;
     466          code_loc = (void *)ramtest_exec;
     467          if ((ram_base < ram_end) &&
     468            !((ram_base <= code_loc) && (code_loc < ram_end))) {           
     469            ramtest_exec(ram_base,ram_end);
     470          }
     471        }
     472#endif
     473        /*
     474         * Step 13: Copy  the exception vector table to system RAM
     475         */
     476        m68k_get_vbr (vbr);
     477        for (i = 0; i < 256; ++i)
     478                M68Kvec[i] = vbr[i];
     479        m68k_set_vbr (M68Kvec);
     480       
     481        /*
     482         * Step 14: More system initialization
     483         * SDCR (Serial DMA configuration register)
     484         *      Disable SDMA during FREEZE
     485         *      Give SDMA priority over all interrupt handlers
     486         *      Set DMA arbiration level to 4
     487         * CICR (CPM interrupt configuration register):
     488         *      SCC1 requests at SCCa position
     489         *      SCC2 requests at SCCb position
     490         *      SCC3 requests at SCCc position
     491         *      SCC4 requests at SCCd position
     492         *      Interrupt request level 4
     493         *      Maintain original priority order
     494         *      Vector base 128
     495         *      SCCs priority grouped at top of table
     496         */
     497        m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
     498        m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
     499                                                (4 << 13) | (0x1F << 8) | (128);
     500
     501        /*
     502         * Step 15: Set module configuration register
     503         *      Disable timers during FREEZE
     504         *      Enable bus monitor during FREEZE
     505         *      BCLRO* arbitration level 3
     506         *      No show cycles
     507         *      User/supervisor access
     508         *      Bus clear interupt service level 7
     509         *      SIM60 interrupt sources higher priority than CPM
     510         */
     511        m360.mcr = 0x4C7F;
    337512
    338513#elif (defined (GEN68360_WITH_SRAM))
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