Changeset 69bde47 in rtems


Ignore:
Timestamp:
Apr 5, 2021, 9:28:10 PM (5 weeks ago)
Author:
Kinsey Moore <kinsey.moore@…>
Branches:
master
Children:
0e49372a
Parents:
3ea43bc
git-author:
Kinsey Moore <kinsey.moore@…> (04/05/21 21:28:10)
git-committer:
Joel Sherrill <joel@…> (04/19/21 15:51:02)
Message:

cpukit/aarch64: Restore ISR cookie bit mask

The _CPU_ISR_Is_enabled() function operates on ISR cookies and so must
mask off the appropriate status bits. This also fixes the naming of the
parameters of the _CPU_ISR_* functions to indicate use of ISR cookies
instead of interrupt enable/disable levels.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/aarch64/include/rtems/score/cpu.h

    r3ea43bc r69bde47  
    211211#if defined(AARCH64_DISABLE_INLINE_ISR_DISABLE_ENABLE)
    212212uint64_t AArch64_interrupt_disable( void );
    213 void AArch64_interrupt_enable( uint64_t level );
    214 void AArch64_interrupt_flash( uint64_t level );
     213void AArch64_interrupt_enable( uint64_t isr_cookie );
     214void AArch64_interrupt_flash( uint64_t isr_cookie );
    215215#else
    216216static inline uint64_t AArch64_interrupt_disable( void )
    217217{
    218   uint64_t level;
     218  uint64_t isr_cookie;
    219219
    220220  __asm__ volatile (
    221     "mrs %[level], DAIF\n"
     221    "mrs %[isr_cookie], DAIF\n"
    222222    "msr DAIFSet, #0x2\n"
    223     : [level] "=&r" (level)
     223    : [isr_cookie] "=&r" (isr_cookie)
    224224  );
    225225
    226   return level;
    227 }
    228 
    229 static inline void AArch64_interrupt_enable( uint64_t level )
     226  return isr_cookie;
     227}
     228
     229static inline void AArch64_interrupt_enable( uint64_t isr_cookie )
    230230{
    231231  __asm__ volatile (
    232     "msr DAIF, %[level]\n"
    233     : : [level] "r" (level)
     232    "msr DAIF, %[isr_cookie]\n"
     233    : : [isr_cookie] "r" (isr_cookie)
    234234  );
    235235}
    236236
    237 static inline void AArch64_interrupt_flash( uint64_t level )
    238 {
    239   AArch64_interrupt_enable(level);
     237static inline void AArch64_interrupt_flash( uint64_t isr_cookie )
     238{
     239  AArch64_interrupt_enable(isr_cookie);
    240240  AArch64_interrupt_disable();
    241241}
     
    253253  AArch64_interrupt_flash( _isr_cookie )
    254254
    255 RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint64_t level )
    256 {
    257   return level == 0;
     255RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint64_t isr_cookie )
     256{
     257  return ( isr_cookie & AARCH64_PSTATE_I ) == 0;
    258258}
    259259
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