Changeset 694e79a0 in rtems


Ignore:
Timestamp:
Jun 28, 2018, 6:20:47 AM (10 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
995e91e8
Parents:
afb60eb
git-author:
Sebastian Huber <sebastian.huber@…> (06/28/18 06:20:47)
git-committer:
Sebastian Huber <sebastian.huber@…> (06/29/18 08:04:38)
Message:

riscv: Add TLS support

Update #3433.

Location:
cpukit/score/cpu/riscv
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/riscv/riscv-context-initialize.c

    rafb60eb r694e79a0  
    3636#include <rtems/score/cpu.h>
    3737#include <rtems/score/address.h>
     38#include <rtems/score/tls.h>
    3839
    3940void _CPU_Context_Initialize(
     
    5556  context->sp = (uintptr_t) stack;
    5657  context->isr_dispatch_disable = 0;
     58
     59  if ( tls_area != NULL ) {
     60    void *tls_block;
     61
     62    tls_block = _TLS_TCB_before_TLS_block_initialize( tls_area );
     63    context->tp = (uintptr_t) tls_block;
     64  }
    5765}
  • cpukit/score/cpu/riscv/riscv-context-switch.S

    rafb60eb r694e79a0  
    6868        LREG    ra, RISCV_CONTEXT_RA(a1)
    6969        LREG    sp, RISCV_CONTEXT_SP(a1)
     70        LREG    tp, RISCV_CONTEXT_TP(a1)
    7071        LREG    s0, RISCV_CONTEXT_S0(a1)
    7172        LREG    s1, RISCV_CONTEXT_S1(a1)
Note: See TracChangeset for help on using the changeset viewer.