Changeset 6937dfd6 in rtems


Ignore:
Timestamp:
May 24, 2001, 7:49:31 PM (19 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
7c05d28
Parents:
44ce2da1
Message:

2000-05-24 Joel Sherrill <joel@…>

  • rtems/score/mips.h: Added constants for MIPS exception numbers. All exceptions should be given low numbers and thus can be installed and processed in a uniform manner. Variances between various MIPS ISA levels were not accounted for.
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/mips/rtems/score/mips.h

    r44ce2da1 r6937dfd6  
    7777
    7878/*
     79 *  RTEMS Vector numbers for exception conditions.  This is a direct
     80 *  map to the causes.
     81 */
     82
     83#define MIPS_EXCEPTION_BASE 0
     84
     85#define MIPS_EXCEPTION_INT              MIPS_EXCEPTION_BASE+0
     86#define MIPS_EXCEPTION_MOD              MIPS_EXCEPTION_BASE+1
     87#define MIPS_EXCEPTION_TLBL             MIPS_EXCEPTION_BASE+2
     88#define MIPS_EXCEPTION_TLBS             MIPS_EXCEPTION_BASE+3
     89#define MIPS_EXCEPTION_ADEL             MIPS_EXCEPTION_BASE+4
     90#define MIPS_EXCEPTION_ADES             MIPS_EXCEPTION_BASE+5
     91#define MIPS_EXCEPTION_IBE              MIPS_EXCEPTION_BASE+6
     92#define MIPS_EXCEPTION_DBE              MIPS_EXCEPTION_BASE+7
     93#define MIPS_EXCEPTION_SYSCALL          MIPS_EXCEPTION_BASE+8
     94#define MIPS_EXCEPTION_BREAK            MIPS_EXCEPTION_BASE+9
     95#define MIPS_EXCEPTION_RI               MIPS_EXCEPTION_BASE+10
     96#define MIPS_EXCEPTION_CPU              MIPS_EXCEPTION_BASE+11
     97#define MIPS_EXCEPTION_OVERFLOW         MIPS_EXCEPTION_BASE+12
     98#define MIPS_EXCEPTION_TRAP             MIPS_EXCEPTION_BASE+13
     99#define MIPS_EXCEPTION_VCEI             MIPS_EXCEPTION_BASE+14
     100/* FPE only on mips2 and higher */
     101#define MIPS_EXCEPTION_FPE              MIPS_EXCEPTION_BASE+15
     102#define MIPS_EXCEPTION_C2E              MIPS_EXCEPTION_BASE+16
     103/* 17-22 reserved */
     104#define MIPS_EXCEPTION_WATCH            MIPS_EXCEPTION_BASE+23
     105/* 24-30 reserved */
     106#define MIPS_EXCEPTION_VCED             MIPS_EXCEPTION_BASE+31
     107
     108#define MIPS_INTERRUPT_BASE             MIPS_EXCEPTION_BASE+32
     109
     110/*
    79111 *  Some macros to access registers
    80112 */
     
    92124
    93125
    94 
    95 
     126/*
     127 *  Access the Cause register
     128 */
    96129
    97130#define mips_get_cause( _x ) \
     
    108141
    109142
    110 
    111 
     143/*
     144 *  Access FCR31
     145 */
    112146
    113147#define mips_get_fcr31( _x ) \
     
    122156    asm volatile( "ctc1 %0, $31; nop" : : "r" (__x) ); \
    123157  } while(0)
    124 
    125 
    126 
    127158
    128159
  • cpukit/score/cpu/mips/rtems/score/mips.h

    r44ce2da1 r6937dfd6  
    7777
    7878/*
     79 *  RTEMS Vector numbers for exception conditions.  This is a direct
     80 *  map to the causes.
     81 */
     82
     83#define MIPS_EXCEPTION_BASE 0
     84
     85#define MIPS_EXCEPTION_INT              MIPS_EXCEPTION_BASE+0
     86#define MIPS_EXCEPTION_MOD              MIPS_EXCEPTION_BASE+1
     87#define MIPS_EXCEPTION_TLBL             MIPS_EXCEPTION_BASE+2
     88#define MIPS_EXCEPTION_TLBS             MIPS_EXCEPTION_BASE+3
     89#define MIPS_EXCEPTION_ADEL             MIPS_EXCEPTION_BASE+4
     90#define MIPS_EXCEPTION_ADES             MIPS_EXCEPTION_BASE+5
     91#define MIPS_EXCEPTION_IBE              MIPS_EXCEPTION_BASE+6
     92#define MIPS_EXCEPTION_DBE              MIPS_EXCEPTION_BASE+7
     93#define MIPS_EXCEPTION_SYSCALL          MIPS_EXCEPTION_BASE+8
     94#define MIPS_EXCEPTION_BREAK            MIPS_EXCEPTION_BASE+9
     95#define MIPS_EXCEPTION_RI               MIPS_EXCEPTION_BASE+10
     96#define MIPS_EXCEPTION_CPU              MIPS_EXCEPTION_BASE+11
     97#define MIPS_EXCEPTION_OVERFLOW         MIPS_EXCEPTION_BASE+12
     98#define MIPS_EXCEPTION_TRAP             MIPS_EXCEPTION_BASE+13
     99#define MIPS_EXCEPTION_VCEI             MIPS_EXCEPTION_BASE+14
     100/* FPE only on mips2 and higher */
     101#define MIPS_EXCEPTION_FPE              MIPS_EXCEPTION_BASE+15
     102#define MIPS_EXCEPTION_C2E              MIPS_EXCEPTION_BASE+16
     103/* 17-22 reserved */
     104#define MIPS_EXCEPTION_WATCH            MIPS_EXCEPTION_BASE+23
     105/* 24-30 reserved */
     106#define MIPS_EXCEPTION_VCED             MIPS_EXCEPTION_BASE+31
     107
     108#define MIPS_INTERRUPT_BASE             MIPS_EXCEPTION_BASE+32
     109
     110/*
    79111 *  Some macros to access registers
    80112 */
     
    92124
    93125
    94 
    95 
     126/*
     127 *  Access the Cause register
     128 */
    96129
    97130#define mips_get_cause( _x ) \
     
    108141
    109142
    110 
    111 
     143/*
     144 *  Access FCR31
     145 */
    112146
    113147#define mips_get_fcr31( _x ) \
     
    122156    asm volatile( "ctc1 %0, $31; nop" : : "r" (__x) ); \
    123157  } while(0)
    124 
    125 
    126 
    127158
    128159
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