Changeset 692e5ba in rtems


Ignore:
Timestamp:
Jul 4, 2008, 4:08:26 PM (11 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.9, master
Children:
c2bb3add
Parents:
06a23329
Message:

2008-07-04 Matthew Riek <matthew.riek@…>

  • Makefile.am, README, include/coverhd.h, network/network.c, startup/bspstart.c, startup/cfinit.c, startup/linkcmdsflash: Add cache support for 5329. Fix bug in network driver. Enable the cache in copyback and write-through so we can assume that in BSP.
Location:
c/src/lib/libbsp/m68k/mcf5329
Files:
8 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/m68k/mcf5329/ChangeLog

    r06a23329 r692e5ba  
     12008-07-04      Matthew Riek <matthew.riek@ibiscomputer.com.au>
     2
     3        * Makefile.am, README, include/coverhd.h, network/network.c,
     4        startup/bspstart.c, startup/cfinit.c, startup/linkcmdsflash: Add
     5        cache support for 5329. Fix bug in network driver. Enable the cache
     6        in copyback and write-through so we can assume that in BSP.
     7
    182008-06-23      Joel Sherrill <joel.sherrill@OARcorp.com>
    29
  • c/src/lib/libbsp/m68k/mcf5329/Makefile.am

    r06a23329 r692e5ba  
    5353libbsp_a_LIBADD = \
    5454    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
    55     ../../../libcpu/@RTEMS_CPU@/shared/misc.rel
     55    ../../../libcpu/@RTEMS_CPU@/shared/misc.rel \
     56    ../../../libcpu/@RTEMS_CPU@/mcf532x/cachepd.rel
     57
    5658if HAS_NETWORKING
    5759libbsp_a_LIBADD += network.rel
  • c/src/lib/libbsp/m68k/mcf5329/README

    r06a23329 r692e5ba  
    2626
    2727============================================================================
     28
    2829      Interrupt map
    2930
    30 +-----+-----------------------------------------------------------------------+
    31 |     |                                PRIORITY                               |
    32 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
    33 |LEVEL|    7   |    6   |    5   |    4   |    3   |    2   |    1   |    0   |
    34 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
    35 |  7  |        |        |        |        |        |        |        |        |
    36 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
    37 |  6  |        |        |        |        |        |        |        |        |
    38 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
    39 |  5  |        |        |        |        |        |        |        |        |
    40 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
    41 |  4  | FEC RX | FEC TX |        |        |        |        |        |   PIT  |
    42 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
    43 |  3  | UART 0 | UART 1 | UART 2 |        |        |        |        |        |
    44 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
    45 |  2  |        |        |        |        |        |        |        |        |
    46 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
    47 |  1  |        |        |        |        |        |        |        |        |
    48 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
     31+-----+
     32|     |
     33+-----+
     34|LEVEL|
     35+-----+
     36|  7  |
     37+-----+
     38|  6  |
     39+-----+
     40|  5  |
     41+-----+
     42|  4  | FEC RX, FEC TX, PIT
     43+-----+
     44|  3  | UART 0, UART 1, UART 2
     45+-----+
     46|  2  |
     47+-----+
     48|  1  |
     49+-----+
    4950
    5051============================================================================
    5152      Timings
     53
     54*** TIME TEST 1 ***
     55rtems_semaphore_create 11
     56rtems_semaphore_delete 9
     57rtems_semaphore_obtain: available 0
     58rtems_semaphore_obtain: not available -- NO_WAIT 0
     59rtems_semaphore_release: no waiting tasks 2
     60*** END OF TEST 1 ***
     61
     62*** TIME TEST 2 ***
     63rtems_semaphore_obtain: not available -- caller blocks 14
     64*** END OF TEST 2 ***
     65
     66*** TIME TEST 3 ***
     67rtems_semaphore_release: task readied -- preempts caller 11
     68*** END OF TEST 3 ***
     69
     70*** TIME TEST 4 ***
     71rtems_task_restart: blocked task -- preempts caller 24
     72rtems_task_restart: ready task -- preempts caller 15
     73rtems_semaphore_release: task readied -- returns to caller 3
     74rtems_task_create 40
     75rtems_task_start 7
     76rtems_task_restart: suspended task -- returns to caller 8
     77rtems_task_delete: suspended task 18
     78rtems_task_restart: ready task -- returns to caller 9
     79rtems_task_restart: blocked task -- returns to caller 10
     80rtems_task_delete: blocked task 19
     81*** END OF TEST 4 ***
     82
     83*** TIME TEST 5 ***
     84rtems_task_suspend: calling task 11
     85rtems_task_resume: task readied -- preempts caller 9
     86*** END OF TEST 5 ***
     87
     88*** TIME TEST 6 ***
     89rtems_task_restart: calling task 4
     90rtems_task_suspend: returns to caller 2
     91rtems_task_resume: task readied -- returns to caller 2
     92rtems_task_delete: ready task 19
     93*** END OF TEST 6 ***
     94
     95*** TIME TEST 7 ***
     96rtems_task_restart: suspended task -- preempts caller 15
     97*** END OF TEST 7 ***
     98
     99*** TIME TEST 8 ***
     100rtems_task_set_priority: obtain current priority 1
     101rtems_task_set_priority: returns to caller 2
     102rtems_task_mode: obtain current mode 0
     103rtems_task_mode: no reschedule 0
     104rtems_task_mode: reschedule -- returns to caller 1
     105rtems_task_mode: reschedule -- preempts caller 13
     106rtems_task_set_note 1
     107rtems_task_get_note 1
     108rtems_clock_set 1
     109rtems_clock_get 4
     110*** END OF TEST 8 ***
     111
     112*** TIME TEST 9 ***
     113rtems_message_queue_create 45
     114rtems_message_queue_send: no waiting tasks 2
     115rtems_message_queue_urgent: no waiting tasks 2
     116rtems_message_queue_receive: available 3
     117rtems_message_queue_flush: no messages flushed 1
     118rtems_message_queue_flush: messages flushed 1
     119rtems_message_queue_delete 12
     120*** END OF TEST 9 ***
     121
     122*** TIME TEST 10 ***
     123rtems_message_queue_receive: not available -- NO_WAIT 1
     124rtems_message_queue_receive: not available -- caller blocks 14
     125*** END OF TEST 10 ***
     126
     127*** TIME TEST 11 ***
     128rtems_message_queue_send: task readied -- preempts caller 13
     129*** END OF TEST 11 ***
     130
     131*** TIME TEST 12 ***
     132rtems_message_queue_send: task readied -- returns to caller 5
     133*** END OF TEST 12 ***
     134
     135*** TIME TEST 13 ***
     136rtems_message_queue_urgent: task readied -- preempts caller 13
     137*** END OF TEST 13 ***
     138
     139*** TIME TEST 14 ***
     140rtems_message_queue_urgent: task readied -- returns to caller 5
     141*** END OF TEST 14 ***
     142
     143*** TIME TEST 15 ***
     144rtems_event_receive: obtain current events 0
     145rtems_event_receive: not available -- NO_WAIT 1
     146rtems_event_receive: not available -- caller blocks 12
     147rtems_event_send: no task readied 1
     148rtems_event_receive: available 3
     149rtems_event_send: task readied -- returns to caller 4
     150*** END OF TEST 15 ***
     151
     152*** TIME TEST 16 ***
     153rtems_event_send: task readied -- preempts caller 13
     154*** END OF TEST 16 ***
     155
     156*** TIME TEST 17 ***
     157rtems_task_set_priority: preempts caller 13
     158*** END OF TEST 17 ***
     159
     160*** TIME TEST 18 ***
     161rtems_task_delete: calling task 30
     162*** END OF TEST 18 ***
     163
     164*** TIME TEST 19 ***
     165rtems_signal_catch 2
     166rtems_signal_send: returns to caller 5
     167rtems_signal_send: signal to self 11
     168exit ASR overhead: returns to calling task 6
     169exit ASR overhead: returns to preempting task 11
     170*** END OF TEST 19 ***
     171
     172*** TIME TEST 20 ***
     173rtems_partition_create 15
     174rtems_region_create 20
     175rtems_partition_get_buffer: available 4
     176rtems_partition_get_buffer: not available 1
     177rtems_partition_return_buffer 4
     178rtems_partition_delete 6
     179rtems_region_get_segment: available 6
     180rtems_region_get_segment: not available -- NO_WAIT 5
     181rtems_region_return_segment: no waiting tasks 5
     182rtems_region_get_segment: not available -- caller blocks 29
     183rtems_region_return_segment: task readied -- preempts caller 29
     184rtems_region_return_segment: task readied -- returns to caller 11
     185rtems_region_delete 6
     186rtems_io_initialize 0
     187rtems_io_open 0
     188rtems_io_close 0
     189rtems_io_read 0
     190rtems_io_write 0
     191rtems_io_control 0
     192*** END OF TEST 20 ***
     193
     194*** TIME TEST 21 ***
     195rtems_task_ident 4
     196rtems_message_queue_ident 3
     197rtems_semaphore_ident 4
     198rtems_partition_ident 3
     199rtems_region_ident 3
     200rtems_port_ident 3
     201rtems_timer_ident 3
     202rtems_rate_monotonic_ident 3
     203*** END OF TEST 21 ***
     204
     205*** TIME TEST 22 ***
     206rtems_message_queue_broadcast: task readied -- returns to caller 16
     207rtems_message_queue_broadcast: no waiting tasks 2
     208rtems_message_queue_broadcast: task readied -- preempts caller 12
     209*** END OF TEST 22 ***
     210
     211*** TIME TEST 23 ***
     212rtems_timer_create 2
     213rtems_timer_fire_after: inactive 2
     214rtems_timer_fire_after: active 1
     215rtems_timer_cancel: active 1
     216rtems_timer_cancel: inactive 1
     217rtems_timer_reset: inactive 2
     218rtems_timer_reset: active 2
     219rtems_timer_fire_when: inactive 2
     220rtems_timer_fire_when: active 2
     221rtems_timer_delete: active 2
     222rtems_timer_delete: inactive 2
     223rtems_task_wake_when 13
     224*** END OF TEST 23 ***
     225
     226*** TIME TEST 24 ***
     227rtems_task_wake_after: yield -- returns to caller 0
     228rtems_task_wake_after: yields -- preempts caller 9
     229*** END OF TEST 24 ***
     230
     231*** TIME TEST 25 ***
     232rtems_clock_tick 10
     233*** END OF TEST 25 ***
     234
     235*** TIME TEST 26 ***
     236_ISR_Disable 1
     237_ISR_Flash 0
     238_ISR_Enable 0
     239_Thread_Disable_dispatch 0
     240_Thread_Enable_dispatch 1
     241_Thread_Set_state 4
     242_Thread_Disptach (NO FP) 11
     243context switch: no floating point contexts 5
     244context switch: self 0
     245context switch: to another task 1
     246fp context switch: restore 1st FP task 5
     247fp context switch: save idle, restore initialized 1
     248fp context switch: save idle, restore idle 6
     249fp context switch: save initialized, restore initialized 1
     250_Thread_Resume 5
     251_Thread_Unblock 3
     252_Thread_Ready 2
     253_Thread_Get 0
     254_Semaphore_Get 0
     255_Thread_Get: invalid id 0
     256*** END OF TEST 26 ***
     257
     258*** TIME TEST 27 ***
     259interrupt entry overhead: returns to interrupted task 1
     260interrupt exit overhead: returns to interrupted task 1
     261interrupt entry overhead: returns to nested interrupt 0
     262interrupt exit overhead: returns to nested interrupt 0
     263interrupt entry overhead: returns to preempting task 1
     264interrupt exit overhead: returns to preempting task 9
     265*** END OF TEST 27 ***
     266
     267*** TIME TEST 28 ***
     268rtems_port_create 5
     269rtems_port_external_to_internal 1
     270rtems_port_internal_to_external 1
     271rtems_port_delete 4
     272*** END OF TEST 28 ***
     273
     274*** TIME TEST 29 ***
     275rtems_rate_monotonic_create 8
     276rtems_rate_monotonic_period: initiate period -- returns to caller 14
     277rtems_rate_monotonic_period: obtain status 3
     278rtems_rate_monotonic_cancel 6
     279rtems_rate_monotonic_delete: inactive 7
     280rtems_rate_monotonic_delete: active 3
     281rtems_rate_monotonic_period: conclude periods -- caller blocks 15
     282*** END OF TEST 29 ***
     283
     284
     285*** TIME TEST OVERHEAD ***
     286rtems_shutdown_executive 0
     287rtems_task_create 0
     288rtems_task_ident 0
     289rtems_task_start 0
     290rtems_task_restart 0
     291rtems_task_delete 0
     292rtems_task_suspend 0
     293rtems_task_resume 0
     294rtems_task_set_priority 0
     295rtems_task_mode 0
     296rtems_task_get_note 0
     297rtems_task_set_note 0
     298rtems_task_wake_when 0
     299rtems_task_wake_after 0
     300rtems_interrupt_catch 0
     301rtems_clock_get 0
     302rtems_clock_set 0
     303rtems_clock_tick 0
     304<pause>
     305rtems_timer_create 0
     306rtems_timer_delete 0
     307rtems_timer_ident 0
     308rtems_timer_fire_after 0
     309rtems_timer_fire_when 0
     310rtems_timer_reset 0
     311rtems_timer_cancel 0
     312rtems_semaphore_create 0
     313rtems_semaphore_delete 0
     314rtems_semaphore_ident 0
     315rtems_semaphore_obtain 0
     316rtems_semaphore_release 0
     317rtems_message_queue_create 0
     318rtems_message_queue_ident 0
     319rtems_message_queue_delete 0
     320rtems_message_queue_send 0
     321rtems_message_queue_urgent 0
     322rtems_message_queue_broadcast 0
     323rtems_message_queue_receive 0
     324rtems_message_queue_flush 0
     325<pause>
     326rtems_event_send 0
     327rtems_event_receive 0
     328rtems_signal_catch 0
     329rtems_signal_send 0
     330rtems_partition_create 0
     331rtems_partition_ident 0
     332rtems_partition_delete 0
     333rtems_partition_get_buffer 0
     334rtems_partition_return_buffer 0
     335rtems_region_create 0
     336rtems_region_ident 0
     337rtems_region_delete 0
     338rtems_region_get_segment 0
     339rtems_region_return_segment 0
     340rtems_port_create 0
     341rtems_port_ident 0
     342rtems_port_delete 0
     343rtems_port_external_to_internal 0
     344rtems_port_internal_to_external 0
     345<pause>
     346rtems_io_initialize 0
     347rtems_io_open 0
     348rtems_io_close 0
     349rtems_io_read 0
     350rtems_io_write 0
     351rtems_io_control 0
     352rtems_fatal_error_occurred 0
     353rtems_rate_monotonic_create 0
     354rtems_rate_monotonic_ident 0
     355rtems_rate_monotonic_delete 0
     356rtems_rate_monotonic_cancel 0
     357rtems_rate_monotonic_period 0
     358rtems_multiprocessing_announce 0
     359*** END OF TIME OVERHEAD ***
     360
     361
  • c/src/lib/libbsp/m68k/mcf5329/include/coverhd.h

    r06a23329 r692e5ba  
    4141#define CALLING_OVERHEAD_TASK_GET_NOTE             0
    4242#define CALLING_OVERHEAD_TASK_SET_NOTE             0
    43 #define CALLING_OVERHEAD_TASK_WAKE_WHEN            1
     43#define CALLING_OVERHEAD_TASK_WAKE_WHEN            0
    4444#define CALLING_OVERHEAD_TASK_WAKE_AFTER           0
    4545#define CALLING_OVERHEAD_INTERRUPT_CATCH           0
    46 #define CALLING_OVERHEAD_CLOCK_GET                 1
    47 #define CALLING_OVERHEAD_CLOCK_SET                 1
     46#define CALLING_OVERHEAD_CLOCK_GET                 0
     47#define CALLING_OVERHEAD_CLOCK_SET                 0
    4848#define CALLING_OVERHEAD_CLOCK_TICK                0
    4949
     
    5151#define CALLING_OVERHEAD_TIMER_IDENT               0
    5252#define CALLING_OVERHEAD_TIMER_DELETE              0
    53 #define CALLING_OVERHEAD_TIMER_FIRE_AFTER          1
    54 #define CALLING_OVERHEAD_TIMER_FIRE_WHEN           1
     53#define CALLING_OVERHEAD_TIMER_FIRE_AFTER          0
     54#define CALLING_OVERHEAD_TIMER_FIRE_WHEN           0
    5555#define CALLING_OVERHEAD_TIMER_RESET               0
    5656#define CALLING_OVERHEAD_TIMER_CANCEL              0
  • c/src/lib/libbsp/m68k/mcf5329/network/network.c

    r06a23329 r692e5ba  
    418418      int len = rxBd->length - sizeof(uint32_t);;
    419419
    420       /*
    421        * Invalidate the cache and push the packet up.
    422        * The cache is so small that it's more efficient to just
    423        * invalidate the whole thing unless the packet is very small.
    424        */
    425420      m = sc->rxMbuf[rxBdIndex];
    426       if (len < 128)
    427         rtems_cache_invalidate_multiple_data_lines(m->m_data, len);
    428       else
    429         rtems_cache_invalidate_entire_data();
     421
     422      rtems_cache_invalidate_multiple_data_lines(m->m_data, len);
     423
    430424      m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header);
    431425      eh = mtod(m, struct ether_header *);
     
    543537        sc->txRealign++;
    544538      }
     539
    545540      txBd->buffer = p;
    546541      txBd->length = m->m_len;
     542     
     543      rtems_cache_flush_multiple_data_lines(txBd->buffer, txBd->length);
     544     
    547545      sc->txMbuf[sc->txBdHead] = m;
    548546      nAdded++;
  • c/src/lib/libbsp/m68k/mcf5329/startup/bspstart.c

    r06a23329 r692e5ba  
    2323
    2424#include <bsp.h>
    25 #include <rtems/libio.h>
    26 #include <rtems/libcsupport.h>
    27 
    28 /*
    29  * Cannot be frozen
    30  */
    31 void _CPU_cache_freeze_data(void)
    32 {
    33 }
    34 void _CPU_cache_unfreeze_data(void)
    35 {
    36 }
    37 void _CPU_cache_freeze_instruction(void)
    38 {
    39 }
    40 void _CPU_cache_unfreeze_instruction(void)
    41 {
    42 }
    43 
    44 /*
    45  * Write-through data cache -- flushes are unnecessary
    46  */
    47 void _CPU_cache_flush_1_data_line(const void *d_addr)
    48 {
    49 }
    50 void _CPU_cache_flush_entire_data(void)
    51 {
    52 }
    53 
    54 void _CPU_cache_enable_instruction(void)
    55 {
    56 }
    57 void _CPU_cache_disable_instruction(void)
    58 {
    59 }
    60 void _CPU_cache_invalidate_entire_instruction(void)
    61 {
    62 }
    63 void _CPU_cache_invalidate_1_instruction_line(const void *addr)
    64 {
    65 }
    66 
    67 void _CPU_cache_enable_data(void)
    68 {
    69 }
    70 void _CPU_cache_disable_data(void)
    71 {
    72 }
    73 void _CPU_cache_invalidate_entire_data(void)
    74 {
    75 }
    76 void _CPU_cache_invalidate_1_data_line(const void *addr)
    77 {
    78 }
     25#include <rtems/rtems/cache.h>
    7926
    8027/*
     
    8532void bsp_start(void)
    8633{
     34  /* cfinit invalidates cache and sets acr registers */
     35
     36  /*
     37   * Enable the cache, we only need to enable the instruction cache as the
     38   * 532x has a unified data and instruction cache.
     39   */
     40  rtems_cache_enable_instruction();
    8741}
    8842
  • c/src/lib/libbsp/m68k/mcf5329/startup/cfinit.c

    r06a23329 r692e5ba  
    44**********************************************************************
    55 Generated by ColdFire Initialisation Utility 2.10.8
    6  Mon Jun 16 10:41:41 2008
     6 Wed Jul 02 14:26:25 2008
    77   
    88 MicroAPL Ltd makes no warranties in respect of the suitability
     
    1111 persons making use of this file must make the final evaluation
    1212 as to its suitability and correctness for a particular application.
     13
     14 $Id$
    1315   
    14  $Id$
    1516*/
    1617
     
    3839static void disable_cache(void);
    3940extern void init_clock_config(void) __attribute__ ((section(".ram_code")));
     41static void init_vbr(void);
     42static void init_cache(void);
     43static void init_crossbar(void);
    4044extern void init_chip_selects(void) __attribute__ ((section(".ram_code")));
     45static void init_eport(void);
     46static void init_flexcan(void);
     47static void init_dma_timers(void);
     48static void init_interrupt_timers(void);
    4149static void init_real_time_clock(void);
    4250static void init_watchdog_timers(void);
     51static void init_edma(void);
    4352static void init_pin_assignments(void);
    44 extern void init_sdram_controller(void)
     53extern void init_sdram_controller(void) 
    4554  __attribute__ ((section(".ram_code")));
     55static void init_interrupt_controller(void);
    4656
    4757/*********************************************************************
     
    5060void init_main(void)
    5161{
    52   /* Mask all interrupts */
    5362  init_clock_config();
    5463
     
    5968
    6069  /* Initialise individual modules */
     70  init_cache();
     71  init_crossbar();
    6172  init_chip_selects();
     73  init_eport();
     74  init_flexcan();
     75  init_dma_timers();
     76  init_interrupt_timers();
    6277  init_real_time_clock();
    6378  init_watchdog_timers();
     79  init_edma();
    6480  init_pin_assignments();
    6581
    6682  /* Initialise SDRAM controller (must be done after pin assignments) */
    6783  init_sdram_controller();
     84
     85  /* Initialise interrupt controller */
     86  init_interrupt_controller();
    6887}
    6988
     
    108127* init_clock_config - Clock Module                                   *
    109128**********************************************************************/
    110 
    111129void init_clock_config(void)
    112130{
     
    155173
    156174/*********************************************************************
     175* init_cache - Unified (Instruction and Data) Cache                  *
     176**********************************************************************/
     177static void init_cache(void)
     178{
     179  /* ACR0: Cache accesses to 32 MB memory region at address $40000000
     180     CACR: Don't cache accesses to the rest of memory
     181   */
     182  /*
     183   * Cache is enabled in bspstart.c
     184   */
     185#if 0
     186  asm("move.l   #0xa0000600,%d0");
     187  asm("movec    %d0,%CACR");
     188#endif 
     189  asm("move.l   #0x4001c020,%d0");
     190  asm("movec    %d0,%ACR0");
     191  asm("move.l   #0x00000000,%d0");
     192  asm("movec    %d0,%ACR1");
     193}
     194
     195/*********************************************************************
     196* init_crossbar - Cross-Bar Switch (XBS) Module                      *
     197**********************************************************************/
     198static void init_crossbar(void)
     199{
     200  /* XBS settings for FlexBus/SDRAM Controller slave: 
     201     Fixed priority (Core, LCD, eDMA, FEC, USB Host, USB OTG), park on ColdFire Core
     202   */
     203  MCF_XBS_PRS1 = MCF_XBS_PRS_M6(0x5) |
     204    MCF_XBS_PRS_M5(0x4) |
     205    MCF_XBS_PRS_M4(0x1) | MCF_XBS_PRS_M2(0x3) | MCF_XBS_PRS_M1(0x2);
     206  MCF_XBS_CRS1 = 0;
     207
     208  /* XBS settings for SRAM Backdoor slave: 
     209     Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
     210   */
     211  MCF_XBS_PRS4 = MCF_XBS_PRS_M6(0x5) |
     212    MCF_XBS_PRS_M5(0x4) |
     213    MCF_XBS_PRS_M4(0x3) | MCF_XBS_PRS_M2(0x2) | MCF_XBS_PRS_M1(0x1);
     214  MCF_XBS_CRS4 = 0;
     215
     216  /* XBS settings for Cryptography Modules slave: 
     217     Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
     218   */
     219  MCF_XBS_PRS6 = MCF_XBS_PRS_M6(0x5) |
     220    MCF_XBS_PRS_M5(0x4) |
     221    MCF_XBS_PRS_M4(0x3) | MCF_XBS_PRS_M2(0x2) | MCF_XBS_PRS_M1(0x1);
     222  MCF_XBS_CRS6 = 0;
     223
     224  /* XBS settings for On-chip Peripherals slave: 
     225     Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
     226   */
     227  MCF_XBS_PRS7 = MCF_XBS_PRS_M6(0x5) |
     228    MCF_XBS_PRS_M5(0x4) |
     229    MCF_XBS_PRS_M4(0x3) | MCF_XBS_PRS_M2(0x2) | MCF_XBS_PRS_M1(0x1);
     230  MCF_XBS_CRS7 = 0;
     231}
     232
     233/*********************************************************************
    157234* init_chip_selects - Chip Select Module (FlexBus)                   *
    158235**********************************************************************/
    159236void init_chip_selects(void)
    160237{
     238  /* Chip Select 1 disabled (CSMR1[V] = 0) */
     239  MCF_FBCS1_CSMR = 0;
     240
     241  /* Chip Select 2 disabled (CSMR2[V] = 0) */
     242  MCF_FBCS2_CSMR = 0;
     243
     244  /* Chip Select 3 disabled (CSMR3[V] = 0) */
     245  MCF_FBCS3_CSMR = 0;
     246
     247  /* Chip Select 4 disabled (CSMR4[V] = 0) */
     248  MCF_FBCS4_CSMR = 0;
     249
     250  /* Chip Select 5 disabled (CSMR5[V] = 0) */
     251  MCF_FBCS5_CSMR = 0;
     252
    161253  /* Chip Select 0: 2 MB of Flash at base address $00000000
    162254     Port size = 16 bits
     
    165257     Address is held for 1 clock at end of read and write cycles
    166258   */
     259  MCF_FBCS0_CSAR = 0;
    167260  MCF_FBCS0_CSCR = MCF_FBCS_CSCR_WS(0x7) |
    168261    (0x1 << 9) | MCF_FBCS_CSCR_AA | MCF_FBCS_CSCR_PS(0x2) | MCF_FBCS_CSCR_BEM;
    169262  MCF_FBCS0_CSMR = MCF_FBCS_CSMR_BAM(0x1f) | MCF_FBCS_CSMR_V;
     263}
     264
     265/*********************************************************************
     266* init_eport - Edge Port Module (EPORT)                              *
     267**********************************************************************/
     268static void init_eport(void)
     269{
     270  /* Pins 1-7 configured as GPIO inputs */
     271  MCF_EPORT_EPPAR = 0;
     272  MCF_EPORT_EPDDR = 0;
     273  MCF_EPORT_EPIER = 0;
     274}
     275
     276/*********************************************************************
     277* init_flexcan - FlexCAN Module                                      *
     278**********************************************************************/
     279static void init_flexcan(void)
     280{
     281  /* FlexCAN controller disabled (CANMCR0[MDIS]=1) */
     282  MCF_CAN_IMASK = 0;
     283  MCF_CAN_RXGMASK = MCF_CAN_RXGMASK_MI(0x1fffffff);
     284  MCF_CAN_RX14MASK = MCF_CAN_RX14MASK_MI(0x1fffffff);
     285  MCF_CAN_RX15MASK = MCF_CAN_RX15MASK_MI(0x1fffffff);
     286  MCF_CAN_CANCTRL = 0;
     287  MCF_CAN_CANMCR = MCF_CAN_CANMCR_MDIS |
     288    MCF_CAN_CANMCR_FRZ |
     289    MCF_CAN_CANMCR_HALT | MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB(0xf);
    170290}
    171291
     
    261381
    262382/*********************************************************************
     383* init_dma_timers - DMA Timers                                       *
     384**********************************************************************/
     385static void init_dma_timers(void)
     386{
     387  /* DMA Timer 0 disabled (DTMR0[RST] = 0) */
     388  MCF_DTIM0_DTMR = 0;
     389  MCF_DTIM0_DTXMR = 0;
     390  MCF_DTIM0_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
     391
     392  /* DMA Timer 1 disabled (DTMR1[RST] = 0) */
     393  MCF_DTIM1_DTMR = 0;
     394  MCF_DTIM1_DTXMR = 0;
     395  MCF_DTIM1_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
     396
     397  /* DMA Timer 2 disabled (DTMR2[RST] = 0) */
     398  MCF_DTIM2_DTMR = 0;
     399  MCF_DTIM2_DTXMR = 0;
     400  MCF_DTIM2_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
     401
     402  /* DMA Timer 3 disabled (DTMR3[RST] = 0) */
     403  MCF_DTIM3_DTMR = 0;
     404  MCF_DTIM3_DTXMR = 0;
     405  MCF_DTIM3_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
     406}
     407
     408/*********************************************************************
     409* init_interrupt_timers - Programmable Interrupt Timers (PIT)        *
     410**********************************************************************/
     411static void init_interrupt_timers(void)
     412{
     413  /* PIT0 disabled (PCSR0[EN]=0) */
     414  MCF_PIT0_PCSR = 0;
     415
     416  /* PIT1 disabled (PCSR1[EN]=0) */
     417  MCF_PIT1_PCSR = 0;
     418
     419  /* PIT2 disabled (PCSR2[EN]=0) */
     420  MCF_PIT2_PCSR = 0;
     421
     422  /* PIT3 disabled (PCSR3[EN]=0) */
     423  MCF_PIT3_PCSR = 0;
     424}
     425
     426/*********************************************************************
    263427* init_real_time_clock - Real-Time Clock (RTC)                       *
    264428**********************************************************************/
     
    279443   */
    280444  MCF_WTM_WCR = MCF_WTM_WCR_WAIT | MCF_WTM_WCR_DOZE | MCF_WTM_WCR_HALTED;
     445  MCF_WTM_WMR = MCF_WTM_WMR_WM(0xffff);
    281446
    282447  /* Core watchdog timer disabled */
    283448  MCF_SCM_CWCR = MCF_SCM_CWCR_CWT(0x8);
     449}
     450
     451/*********************************************************************
     452* init_edma - eDMA Controller                                        *
     453**********************************************************************/
     454static void init_edma(void)
     455{
     456  /* Associate eDMA channels 9-12 with SSI signals */
     457  MCF_CCM_MISCCR &= ~MCF_CCM_MISCCR_TIM_DMA;
     458
     459  /* Configured for round-robin arbitration mode */
     460  MCF_EDMA_CR = MCF_EDMA_CR_ERCA;
     461
     462  /* All error interrupts are disabled */
     463  MCF_EDMA_EEI = 0;
     464
     465  /* All DMA requests from peripherals are masked */
     466  MCF_EDMA_ERQ = 0;
     467}
     468
     469/*********************************************************************
     470* init_interrupt_controller - Interrupt Controller                   *
     471**********************************************************************/
     472static void init_interrupt_controller(void)
     473{
     474  /* No interrupt sources configured */
     475  MCF_INTC1_ICR0 = 0;
     476  MCF_INTC1_ICR1 = 0;
     477  MCF_INTC1_ICR3 = 0;
     478  MCF_INTC1_ICR4 = 0;
     479  MCF_INTC1_ICR5 = 0;
     480  MCF_INTC1_ICR6 = 0;
     481  MCF_INTC1_ICR7 = 0;
     482  MCF_INTC1_ICR8 = 0;
     483  MCF_INTC1_ICR9 = 0;
     484  MCF_INTC1_ICR10 = 0;
     485  MCF_INTC1_ICR11 = 0;
     486  MCF_INTC1_ICR12 = 0;
     487  MCF_INTC1_ICR13 = 0;
     488  MCF_INTC1_ICR14 = 0;
     489  MCF_INTC1_ICR15 = 0;
     490  MCF_INTC1_ICR16 = 0;
     491  MCF_INTC1_ICR17 = 0;
     492  MCF_INTC1_ICR18 = 0;
     493  MCF_INTC1_ICR19 = 0;
     494  MCF_INTC1_ICR40 = 0;
     495  MCF_INTC1_ICR41 = 0;
     496  MCF_INTC1_ICR42 = 0;
     497  MCF_INTC1_ICR43 = 0;
     498  MCF_INTC1_ICR44 = 0;
     499  MCF_INTC1_ICR45 = 0;
     500  MCF_INTC1_ICR46 = 0;
     501  MCF_INTC1_ICR47 = 0;
     502  MCF_INTC1_ICR48 = 0;
     503  MCF_INTC1_ICR49 = 0;
     504  MCF_INTC1_ICR50 = 0;
     505  MCF_INTC1_ICR51 = 0;
     506  MCF_INTC1_ICR52 = 0;
     507  MCF_INTC1_ICR53 = 0;
     508  MCF_INTC0_ICR1 = 0;
     509  MCF_INTC0_ICR2 = 0;
     510  MCF_INTC0_ICR3 = 0;
     511  MCF_INTC0_ICR4 = 0;
     512  MCF_INTC0_ICR5 = 0;
     513  MCF_INTC0_ICR6 = 0;
     514  MCF_INTC0_ICR7 = 0;
     515  MCF_INTC0_ICR8 = 0;
     516  MCF_INTC0_ICR9 = 0;
     517  MCF_INTC0_ICR10 = 0;
     518  MCF_INTC0_ICR11 = 0;
     519  MCF_INTC0_ICR12 = 0;
     520  MCF_INTC0_ICR13 = 0;
     521  MCF_INTC0_ICR14 = 0;
     522  MCF_INTC0_ICR15 = 0;
     523  MCF_INTC0_ICR16 = 0;
     524  MCF_INTC0_ICR17 = 0;
     525  MCF_INTC0_ICR18 = 0;
     526  MCF_INTC0_ICR19 = 0;
     527  MCF_INTC0_ICR20 = 0;
     528  MCF_INTC0_ICR21 = 0;
     529  MCF_INTC0_ICR22 = 0;
     530  MCF_INTC0_ICR23 = 0;
     531  MCF_INTC0_ICR24 = 0;
     532  MCF_INTC0_ICR25 = 0;
     533  MCF_INTC0_ICR26 = 0;
     534  MCF_INTC0_ICR27 = 0;
     535  MCF_INTC0_ICR28 = 0;
     536  MCF_INTC0_ICR30 = 0;
     537  MCF_INTC0_ICR31 = 0;
     538  MCF_INTC0_ICR32 = 0;
     539  MCF_INTC0_ICR33 = 0;
     540  MCF_INTC0_ICR34 = 0;
     541  MCF_INTC0_ICR35 = 0;
     542  MCF_INTC0_ICR36 = 0;
     543  MCF_INTC0_ICR37 = 0;
     544  MCF_INTC0_ICR38 = 0;
     545  MCF_INTC0_ICR39 = 0;
     546  MCF_INTC0_ICR40 = 0;
     547  MCF_INTC0_ICR41 = 0;
     548  MCF_INTC0_ICR42 = 0;
     549  MCF_INTC0_ICR43 = 0;
     550  MCF_INTC0_ICR44 = 0;
     551  MCF_INTC0_ICR45 = 0;
     552  MCF_INTC0_ICR46 = 0;
     553  MCF_INTC0_ICR47 = 0;
     554  MCF_INTC0_ICR48 = 0;
     555  MCF_INTC0_ICR62 = 0;
     556  MCF_INTC0_IMRH = 0xffffffff;
     557  MCF_INTC0_IMRL = 0xffffffff;
     558  MCF_INTC1_IMRH = 0xffffffff;
     559  MCF_INTC1_IMRL = 0xffffffff;
    284560}
    285561
  • c/src/lib/libbsp/m68k/mcf5329/startup/linkcmdsflash

    r06a23329 r692e5ba  
    135135        PROVIDE( _data_dest_start = . );
    136136        PROVIDE( _copy_start = .);
    137         *(.data)
     137        *(.data*)
    138138        *(.gnu.linkonce.d*)
    139139        *(.gcc_except_table*)
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