Changeset 68e60ddb in rtems


Ignore:
Timestamp:
Jun 7, 2011, 8:23:44 AM (8 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
1343dfa3
Parents:
25874f0
Message:

2011-06-07 Sebastian Huber <sebastian.huber@…>

  • shared/src/cache_.h: Moved implementation from "cache.c" to here. This avoids the function call overhead.
  • shared/src/cache.c: Removed file.
  • Makefile.am: Reflect changes above.
Location:
c/src/lib/libcpu/powerpc
Files:
1 deleted
3 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/powerpc/ChangeLog

    r25874f0 r68e60ddb  
     12011-06-07      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * shared/src/cache_.h: Moved implementation from "cache.c" to here.
     4        This avoids the function call overhead.
     5        * shared/src/cache.c: Removed file.
     6        * Makefile.am: Reflect changes above.
     7
    182011-06-07      Sebastian Huber <sebastian.huber@embedded-brains.de>
    29
  • c/src/lib/libcpu/powerpc/Makefile.am

    r25874f0 r68e60ddb  
    7575# shared/cache
    7676noinst_PROGRAMS += shared/cache.rel
    77 shared_cache_rel_SOURCES = shared/src/cache.c shared/src/cache_.h \
     77shared_cache_rel_SOURCES = shared/src/cache_.h \
    7878    ../shared/src/cache_aligned_malloc.c ../shared/src/cache_manager.c \
    7979    ../shared/include/cache.h
  • c/src/lib/libcpu/powerpc/shared/src/cache_.h

    r25874f0 r68e60ddb  
    77 */
    88
     9/*
     10 *  Cache Management Support Routines for the MC68040
     11 * Modified for MPC8260 Andy Dachs <a.dachs@sstl.co.uk>
     12 * Surrey Satellite Technology Limited (SSTL), 2001
     13 *
     14 *  $Id$
     15 */
     16
    917#ifndef LIBCPU_POWERPC_CACHE_H
    1018#define LIBCPU_POWERPC_CACHE_H
    1119
     20#include <rtems.h>
    1221#include <rtems/powerpc/powerpc.h>
    13 #include <libcpu/cache.h>
     22#include <rtems/powerpc/registers.h>
    1423
    1524/* Provide the CPU defines only if we have a cache */
     
    1928#endif
    2029
     30/*
     31 * CACHE MANAGER: The following functions are CPU-specific.
     32 * They provide the basic implementation for the rtems_* cache
     33 * management routines. If a given function has no meaning for the CPU,
     34 * it does nothing by default.
     35 *
     36 * FIXME: Some functions simply have not been implemented.
     37 */
     38
     39#if defined(ppc603) || defined(ppc603e) || defined(mpc8260) /* And possibly others */
     40
     41/* Helpful macros */
     42#define PPC_Get_HID0( _value ) \
     43  do { \
     44      _value = 0;        /* to avoid warnings */ \
     45      __asm__ volatile( \
     46          "mfspr %0, 0x3f0;"     /* get HID0 */ \
     47          "isync" \
     48          : "=r" (_value) \
     49          : "0" (_value) \
     50      ); \
     51  } while (0)
     52
     53#define PPC_Set_HID0( _value ) \
     54  do { \
     55      __asm__ volatile( \
     56          "isync;" \
     57          "mtspr 0x3f0, %0;"     /* load HID0 */ \
     58          "isync" \
     59          : "=r" (_value) \
     60          : "0" (_value) \
     61      ); \
     62  } while (0)
     63
     64static inline void _CPU_cache_enable_data(void)
     65{
     66  uint32_t   value;
     67  PPC_Get_HID0( value );
     68  value |= HID0_DCE;        /* set DCE bit */
     69  PPC_Set_HID0( value );
     70}
     71
     72static inline void _CPU_cache_disable_data(void)
     73{
     74  uint32_t   value;
     75  PPC_Get_HID0( value );
     76  value &= ~HID0_DCE;        /* clear DCE bit */
     77  PPC_Set_HID0( value );
     78}
     79
     80static inline void _CPU_cache_invalidate_entire_data(void)
     81{
     82  uint32_t  value;
     83  PPC_Get_HID0( value );
     84  value |= HID0_DCI;        /* set data flash invalidate bit */
     85  PPC_Set_HID0( value );
     86  value &= ~HID0_DCI;        /* clear data flash invalidate bit */
     87  PPC_Set_HID0( value );
     88}
     89
     90static inline void _CPU_cache_freeze_data(void)
     91{
     92  uint32_t  value;
     93  PPC_Get_HID0( value );
     94  value |= HID0_DLOCK;        /* set data cache lock bit */
     95  PPC_Set_HID0( value );
     96}
     97
     98static inline void _CPU_cache_unfreeze_data(void)
     99{
     100  uint32_t  value;
     101  PPC_Get_HID0( value );
     102  value &= ~HID0_DLOCK;        /* set data cache lock bit */
     103  PPC_Set_HID0( value );
     104}
     105
     106static inline void _CPU_cache_flush_entire_data(void)
     107{
     108  /*
     109   * FIXME: how can we do this?
     110   */
     111}
     112
     113static inline void _CPU_cache_enable_instruction(void)
     114{
     115  uint32_t   value;
     116  PPC_Get_HID0( value );
     117  value |= 0x00008000;       /* Set ICE bit */
     118  PPC_Set_HID0( value );
     119}
     120
     121static inline void _CPU_cache_disable_instruction(void)
     122{
     123  uint32_t   value;
     124  PPC_Get_HID0( value );
     125  value &= 0xFFFF7FFF;       /* Clear ICE bit */
     126  PPC_Set_HID0( value );
     127}
     128
     129static inline void _CPU_cache_invalidate_entire_instruction(void)
     130{
     131  uint32_t  value;
     132  PPC_Get_HID0( value );
     133  value |= HID0_ICFI;        /* set data flash invalidate bit */
     134  PPC_Set_HID0( value );
     135  value &= ~HID0_ICFI;        /* clear data flash invalidate bit */
     136  PPC_Set_HID0( value );
     137}
     138
     139static inline void _CPU_cache_freeze_instruction(void)
     140{
     141  uint32_t  value;
     142  PPC_Get_HID0( value );
     143  value |= HID0_ILOCK;        /* set instruction cache lock bit */
     144  PPC_Set_HID0( value );
     145}
     146
     147static inline void _CPU_cache_unfreeze_instruction(void)
     148{
     149  uint32_t  value;
     150  PPC_Get_HID0( value );
     151  value &= ~HID0_ILOCK;        /* set instruction cache lock bit */
     152  PPC_Set_HID0( value );
     153}
     154
     155#elif ( defined(mpx8xx) || defined(mpc860) || defined(mpc821) )
     156
     157#define mtspr(_spr,_reg) \
     158  __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) )
     159#define isync \
     160  __asm__ volatile ("isync\n"::)
     161
     162static inline void _CPU_cache_flush_entire_data(void) {}
     163static inline void _CPU_cache_invalidate_entire_data(void) {}
     164static inline void _CPU_cache_freeze_data(void) {}
     165static inline void _CPU_cache_unfreeze_data(void) {}
     166
     167static inline void _CPU_cache_enable_data(void)
     168{
     169  uint32_t   r1;
     170  r1 = (0x2<<24);
     171  mtspr( 568, r1 );
     172  isync;
     173}
     174
     175static inline void _CPU_cache_disable_data(void)
     176{
     177  uint32_t   r1;
     178  r1 = (0x4<<24);
     179  mtspr( 568, r1 );
     180  isync;
     181}
     182
     183static inline void _CPU_cache_invalidate_entire_instruction(void) {}
     184static inline void _CPU_cache_freeze_instruction(void) {}
     185static inline void _CPU_cache_unfreeze_instruction(void) {}
     186
     187static inline void _CPU_cache_enable_instruction(void)
     188{
     189  uint32_t   r1;
     190  r1 = (0x2<<24);
     191  mtspr( 560, r1 );
     192  isync;
     193}
     194
     195static inline void _CPU_cache_disable_instruction(void)
     196{
     197  uint32_t   r1;
     198  r1 = (0x4<<24);
     199  mtspr( 560, r1 );
     200  isync;
     201}
     202
     203#else
     204
     205#warning Most cache functions are not implemented
     206
     207static inline void _CPU_cache_flush_entire_data(void)
     208{
     209        /* Void */
     210}
     211
     212static inline void _CPU_cache_invalidate_entire_data(void)
     213{
     214        /* Void */
     215}
     216
     217static inline void _CPU_cache_freeze_data(void)
     218{
     219        /* Void */
     220}
     221
     222static inline void _CPU_cache_unfreeze_data(void)
     223{
     224        /* Void */
     225}
     226
     227static inline void _CPU_cache_enable_data(void)
     228{
     229        /* Void */
     230}
     231
     232static inline void _CPU_cache_disable_data(void)
     233{
     234        /* Void */
     235}
     236
     237static inline void _CPU_cache_invalidate_entire_instruction(void)
     238{
     239        /* Void */
     240}
     241
     242static inline void _CPU_cache_freeze_instruction(void)
     243{
     244        /* Void */
     245}
     246
     247static inline void _CPU_cache_unfreeze_instruction(void)
     248{
     249        /* Void */
     250}
     251
     252static inline void _CPU_cache_enable_instruction(void)
     253{
     254        /* Void */
     255}
     256
     257static inline void _CPU_cache_disable_instruction(void)
     258{
     259        /* Void */
     260}
     261
     262#endif
     263
     264static inline void _CPU_cache_invalidate_1_data_line(const void *addr)
     265{
     266  __asm__ volatile ( "dcbi 0,%0" :: "r" (addr) : "memory" );
     267}
     268
     269static inline void _CPU_cache_flush_1_data_line(const void *addr)
     270{
     271  __asm__ volatile ( "dcbf 0,%0" :: "r" (addr) : "memory" );
     272}
     273
     274
     275static inline void _CPU_cache_invalidate_1_instruction_line(const void *addr)
     276{
     277  __asm__ volatile ( "icbi 0,%0" :: "r" (addr) : "memory");
     278}
     279
    21280#endif /* LIBCPU_POWERPC_CACHE_H */
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