Changeset 66fe6be6 in rtems
- Timestamp:
- 01/05/00 18:40:20 (24 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 54a5ee7
- Parents:
- 69405459
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/m68k/gen68360/startup/init68360.c
r69405459 r66fe6be6 335 335 * Enable bus monitor during FREEZE 336 336 * BCLRO* arbitration level 3 337 338 #elif (defined (GEN68360_WITH_SRAM)) 339 /* 340 *************************************************** 341 * Generic Standalone Motorola 68360 * 342 * As described in MC68360 User's Manual * 343 * But uses SRAM instead of DRAM * 344 * CS0* - 512kx8 flash memory * 345 * CS1* - 512kx32 static RAM * 346 *************************************************** 347 */ 348 349 /* 350 * Step 7: Deal with clock synthesizer 351 * HARDWARE: 352 * Change if you're not using an external oscillator which 353 * oscillates at the system clock rate. 354 */ 355 m360.clkocr = 0x8F; /* No more writes, no clock outputs */ 356 m360.pllcr = 0xD000; /* PLL, no writes, no prescale, 357 no LPSTOP slowdown, PLL X1 */ 358 m360.cdvcr = 0x8000; /* No more writes, no clock division */ 359 360 /* 361 * Step 8: Initialize system protection 362 * Enable watchdog 363 * Watchdog causes system reset 364 * Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator) 365 * Enable double bus fault monitor 366 * Enable bus monitor for external cycles 367 * 1024 clocks for external timeout 368 */ 369 m360.sypcr = 0xEC; 370 371 /* 372 * Step 9: Clear parameter RAM and reset communication processor module 373 */ 374 for (i = 0 ; i < 192 ; i += sizeof (long)) { 375 *((long *)((char *)&m360 + 0xC00 + i)) = 0; 376 *((long *)((char *)&m360 + 0xD00 + i)) = 0; 377 *((long *)((char *)&m360 + 0xE00 + i)) = 0; 378 *((long *)((char *)&m360 + 0xF00 + i)) = 0; 379 } 380 M360ExecuteRISC (M360_CR_RST); 381 382 /* 383 * Step 10: Write PEPAR 384 * SINTOUT not used (CPU32+ mode) 385 * CF1MODE=00 (CONFIG1 input) 386 * IPIPE1* 387 * WE0* - WE3* 388 * OE* output 389 * CAS2* - CAS3* 390 * CAS0* - CAS1* 391 * CS7* 392 * AVEC* 393 * HARDWARE: 394 * Change if you are using a different memory configuration 395 * (static RAM, external address multiplexing, etc). 396 */ 397 m360.pepar = 0x0080; 398 399 /* 400 * Step 11: Set up GMR 401 * 402 */ 403 m360.gmr = 0x0; 404 405 /* 406 * Step 11a: Remap 512Kx8 flash memory on CS0* 407 * 2 wait states 408 * Make it read-only for now 409 */ 410 m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP | 411 M360_MEMC_BR_V; 412 m360.memc[0].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB | 413 M360_MEMC_OR_8BIT; 414 /* 415 * Step 12: Set up main memory 416 * 512Kx32 SRAM on CS1* 417 * 0 wait states 418 */ 419 m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V; 420 m360.memc[1].or = M360_MEMC_OR_WAITS(0) | M360_MEMC_OR_2MB | 421 M360_MEMC_OR_32BIT; 422 /* 423 * Step 13: Copy the exception vector table to system RAM 424 */ 425 m68k_get_vbr (vbr); 426 for (i = 0; i < 256; ++i) 427 M68Kvec[i] = vbr[i]; 428 m68k_set_vbr (M68Kvec); 429 430 /* 431 * Step 14: More system initialization 432 * SDCR (Serial DMA configuration register) 433 * Enable SDMA during FREEZE 434 * Give SDMA priority over all interrupt handlers 435 * Set DMA arbiration level to 4 436 * CICR (CPM interrupt configuration register): 437 * SCC1 requests at SCCa position 438 * SCC2 requests at SCCb position 439 * SCC3 requests at SCCc position 440 * SCC4 requests at SCCd position 441 * Interrupt request level 4 442 * Maintain original priority order 443 * Vector base 128 444 * SCCs priority grouped at top of table 445 */ 446 m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4; 447 m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) | 448 (4 << 13) | (0x1F << 8) | (128); 449 450 /* 451 * Step 15: Set module configuration register 452 * Disable timers during FREEZE 453 * Enable bus monitor during FREEZE 454 * BCLRO* arbitration level 3 455 * No show cycles 456 * User/supervisor access 457 * Bus clear interrupt service level 7 458 * SIM60 interrupt sources higher priority than CPM 459 */ 460 m360.mcr = 0x4C7F; 337 461 * No show cycles 338 462 * User/supervisor access
Note: See TracChangeset
for help on using the changeset viewer.