- Timestamp:
- 03/16/11 20:05:17 (13 years ago)
- Branches:
- 4.11, 5, master
- Children:
- 20546ace
- Parents:
- 06dcaf0
- Location:
- c/src/lib/libbsp/i386
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/i386/ChangeLog
r06dcaf0 r66729db3 1 2011-03-16 Jennifer Averett <jennifer.averett@OARcorp.com> 2 3 PR 1729/cpukit 4 * shared/irq/irq_asm.S: Add next step in SMP support. This adds an 5 allocated array of the Per_CPU structures to support multiple cpus vs 6 a single instance of the structure which is still used if SMP support 7 is disabled. Configuration support is also added to explicitly enable 8 or disable SMP. But SMP can only be enabled for the CPUs which will 9 support it initially -- SPARC and i386. With the stub BSP support, a 10 BSP can be run as a single core SMP system from an RTEMS data 11 structure standpoint. 12 1 13 2011-03-01 Ralf Corsépius <ralf.corsepius@rtems.org> 2 14 -
c/src/lib/libbsp/i386/shared/irq/irq_asm.S
r06dcaf0 r66729db3 4 4 * 5 5 * Copyright (C) 1998 valette@crf.canon.fr 6 * 7 * COPYRIGHT (c) 1989-2011. 8 * On-Line Applications Research Corporation (OAR). 6 9 * 7 10 * The license and distribution terms for this file may be … … 13 16 14 17 #include <rtems/asm.h> 18 #include <rtems/system.h> 15 19 #include <bspopts.h> 16 20 #include <bsp/irq_asm.h> … … 141 145 .check_stack_switch: 142 146 movl esp, ebp /* ebp = previous stack pointer */ 143 144 movl $SYM(_Per_CPU_Information), ebx 147 #if defined(RTEMS_SMP) && defined(BSP_HAS_SMP) 148 movl $SYM(_Per_CPU_Information_p), ebx 149 call SYM(bsp_smp_processor_id) 150 mov (ebx,eax,4), ebx 151 #else 152 movl $SYM(_Per_CPU_Information), ebx 153 #endif 145 154 146 155 /* is this the outermost interrupt? */
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