Changeset 66659ff in rtems-libbsd for freebsd/sys/sh


Ignore:
Timestamp:
Nov 6, 2013, 3:20:21 PM (6 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, afaeccc05a556f6aa25ba044a7e49d6aa634a59e, freebsd-9.3, master
Children:
9ca3faf
Parents:
ce96623
git-author:
Sebastian Huber <sebastian.huber@…> (11/06/13 15:20:21)
git-committer:
Sebastian Huber <sebastian.huber@…> (11/11/13 09:08:08)
Message:

Update to FreeBSD 9.2

Location:
freebsd/sys/sh
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • freebsd/sys/sh/include/machine/in_cksum.h

    rce96623 r66659ff  
    4141#define in_cksum(m, len)        in_cksum_skip(m, len, 0)
    4242
     43#if defined(IPVERSION) && (IPVERSION == 4)
    4344/*
    4445 * It it useful to have an Internet checksum routine which is inlineable
     
    6768
    6869#endif
     70#endif
    6971
    7072#ifdef _KERNEL
     73#if defined(IPVERSION) && (IPVERSION == 4)
    7174u_int in_cksum_hdr(const struct ip *ip);
     75#endif
    7276u_short in_addword(u_short sum, u_short b);
    7377u_short in_pseudo(u_int sum, u_int b, u_int c);
  • freebsd/sys/sh/include/machine/pci_cfgreg.h

    rce96623 r66659ff  
    2828 */
    2929
     30#ifndef __X86_PCI_CFGREG_H__
     31#define __X86_PCI_CFGREG_H__
     32
    3033#define CONF1_ADDR_PORT    0x0cf8
    3134#define CONF1_DATA_PORT    0x0cfc
     
    4447#define CONF2_ENABLE_RES   0x0e
    4548
     49u_long          hostb_alloc_start(int type, u_long start, u_long end, u_long count);
    4650int             pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus);
    4751int             pci_cfgregopen(void);
    4852u_int32_t       pci_cfgregread(int bus, int slot, int func, int reg, int bytes);
    4953void            pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes);
     54#ifdef __HAVE_PIR
    5055void            pci_pir_open(void);
    5156int             pci_pir_probe(int bus, int require_parse);
    5257int             pci_pir_route_interrupt(int bus, int device, int func, int pin);
     58#endif
     59
     60#endif /* !__X86_PCI_CFGREG_H__ */
  • freebsd/sys/sh/pci/pci_bus.c

    rce96623 r66659ff  
    5454#include <rtems/bsd/local/pcib_if.h>
    5555
    56 #ifndef __rtems__
    57 static int      pcibios_pcib_route_interrupt(device_t pcib, device_t dev,
    58     int pin);
    59 #else /* __rtems__ */
    60 int     pcibios_pcib_route_interrupt(device_t pcib, device_t dev, int pin);
    61 #endif /* __rtems__ */
    62 
    6356int
    6457legacy_pcib_maxslots(device_t dev)
     
    6962/* read configuration space register */
    7063
    71 u_int32_t
     64uint32_t
    7265legacy_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
    7366                        u_int reg, int bytes)
     
    8073void
    8174legacy_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
    82                          u_int reg, u_int32_t data, int bytes)
     75                         u_int reg, uint32_t data, int bytes)
    8376{
    8477        pci_cfgregwrite(bus, slot, func, reg, data, bytes);
     78}
     79
     80/* route interrupt */
     81
     82static int
     83legacy_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
     84{
     85
     86#ifdef __HAVE_PIR
     87        return (pci_pir_route_interrupt(pci_get_bus(dev), pci_get_slot(dev),
     88            pci_get_function(dev), pin));
     89#else
     90        /* No routing possible */
     91        return (PCI_INVALID_IRQ);
     92#endif
    8593}
    8694
     
    136144                          uint8_t *busnum)
    137145{
     146#ifdef __i386__
    138147        const char *s = NULL;
    139148        static uint8_t pxb[4];  /* hack for 450nx */
     
    353362
    354363        return s;
     364#else
     365        const char *s = NULL;
     366
     367        *busnum = 0;
     368        if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
     369                s = "Host to PCI bridge";
     370        return s;
     371#endif
    355372}
    356373
     
    363380{
    364381        int bus, slot, func;
    365         u_int8_t  hdrtype;
     382        uint8_t  hdrtype;
    366383        int found = 0;
    367384        int pcifunchigh;
     
    406423                         * Read the IDs and class from the device.
    407424                         */
    408                         u_int32_t id;
    409                         u_int8_t class, subclass, busnum;
     425                        uint32_t id;
     426                        uint8_t class, subclass, busnum;
    410427                        const char *s;
    411428                        device_t *devs;
     
    494511legacy_pcib_attach(device_t dev)
    495512{
     513#ifdef __HAVE_PIR
    496514        device_t pir;
     515#endif
    497516        int bus;
    498517
     518        bus = pcib_get_bus(dev);
     519#ifdef __HAVE_PIR
    499520        /*
    500521         * Look for a PCI BIOS interrupt routing table as that will be
    501522         * our method of routing interrupts if we have one.
    502523         */
    503         bus = pcib_get_bus(dev);
    504 #ifndef __rtems__
    505524        if (pci_pir_probe(bus, 0)) {
    506525                pir = BUS_ADD_CHILD(device_get_parent(dev), 0, "pir", 0);
     
    508527                        device_probe_and_attach(pir);
    509528        }
    510 #endif /* __rtems__ */
     529#endif
    511530        device_add_child(dev, "pci", bus);
    512531        return bus_generic_attach(dev);
     
    544563}
    545564
     565/*
     566 * Helper routine for x86 Host-PCI bridge driver resource allocation.
     567 * This is used to adjust the start address of wildcard allocation
     568 * requests to avoid low addresses that are known to be problematic.
     569 *
     570 * If no memory preference is given, use upper 32MB slot most BIOSes
     571 * use for their memory window.  This is typically only used on older
     572 * laptops that don't have PCI busses behind a PCI bridge, so assuming
     573 * > 32MB is likely OK.
     574 *     
     575 * However, this can cause problems for other chipsets, so we make
     576 * this tunable by hw.pci.host_mem_start.
     577 */
    546578SYSCTL_DECL(_hw_pci);
    547579
    548 static unsigned long legacy_host_mem_start = 0x80000000;
    549 TUNABLE_ULONG("hw.pci.host_mem_start", &legacy_host_mem_start);
    550 SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN,
    551     &legacy_host_mem_start, 0x80000000,
    552     "Limit the host bridge memory to being above this address.  Must be\n\
    553 set at boot via a tunable.");
     580static unsigned long host_mem_start = 0x80000000;
     581TUNABLE_ULONG("hw.pci.host_mem_start", &host_mem_start);
     582SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN, &host_mem_start,
     583    0, "Limit the host bridge memory to being above this address.");
     584
     585u_long
     586hostb_alloc_start(int type, u_long start, u_long end, u_long count)
     587{
     588
     589        if (start + count - 1 != end) {
     590                if (type == SYS_RES_MEMORY && start < host_mem_start)
     591                        start = host_mem_start;
     592                if (type == SYS_RES_IOPORT && start < 0x1000)
     593                        start = 0x1000;
     594        }
     595        return (start);
     596}
    554597
    555598struct resource *
     
    557600    u_long start, u_long end, u_long count, u_int flags)
    558601{
    559     /*
    560      * If no memory preference is given, use upper 32MB slot most
    561      * bioses use for their memory window.  Typically other bridges
    562      * before us get in the way to assert their preferences on memory.
    563      * Hardcoding like this sucks, so a more MD/MI way needs to be
    564      * found to do it.  This is typically only used on older laptops
    565      * that don't have pci busses behind pci bridge, so assuming > 32MB
    566      * is liekly OK.
    567      *
    568      * However, this can cause problems for other chipsets, so we make
    569      * this tunable by hw.pci.host_mem_start.
    570      */
    571     if (type == SYS_RES_MEMORY && start == 0UL && end == ~0UL)
    572         start = legacy_host_mem_start;
    573     if (type == SYS_RES_IOPORT && start == 0UL && end == ~0UL)
    574         start = 0x1000;
     602
     603    start = hostb_alloc_start(type, start, end, count);
    575604    return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
    576605        count, flags));
     
    601630        DEVMETHOD(pcib_read_config,     legacy_pcib_read_config),
    602631        DEVMETHOD(pcib_write_config,    legacy_pcib_write_config),
    603         DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
     632        DEVMETHOD(pcib_route_interrupt, legacy_pcib_route_interrupt),
    604633        DEVMETHOD(pcib_alloc_msi,       legacy_pcib_alloc_msi),
    605634        DEVMETHOD(pcib_release_msi,     pcib_release_msi),
     
    617646
    618647
    619 #ifndef __rtems__
    620648/*
    621649 * Install placeholder to claim the resources owned by the
     
    666694DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0);
    667695
    668 
     696#ifdef __HAVE_PIR
    669697/*
    670698 * Provide a PCI-PCI bridge driver for PCI busses behind PCI-PCI bridges
     
    677705        /* Device interface */
    678706        DEVMETHOD(device_probe,         pcibios_pcib_probe),
    679         DEVMETHOD(device_attach,        pcib_attach),
    680         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
    681         DEVMETHOD(device_suspend,       bus_generic_suspend),
    682         DEVMETHOD(device_resume,        bus_generic_resume),
    683 
    684         /* Bus interface */
    685         DEVMETHOD(bus_read_ivar,        pcib_read_ivar),
    686         DEVMETHOD(bus_write_ivar,       pcib_write_ivar),
    687         DEVMETHOD(bus_alloc_resource,   pcib_alloc_resource),
    688         DEVMETHOD(bus_release_resource, bus_generic_release_resource),
    689         DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
    690         DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
    691         DEVMETHOD(bus_setup_intr,       bus_generic_setup_intr),
    692         DEVMETHOD(bus_teardown_intr,    bus_generic_teardown_intr),
    693707
    694708        /* pcib interface */
    695         DEVMETHOD(pcib_maxslots,        pcib_maxslots),
    696         DEVMETHOD(pcib_read_config,     pcib_read_config),
    697         DEVMETHOD(pcib_write_config,    pcib_write_config),
    698         DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
    699         DEVMETHOD(pcib_alloc_msi,       pcib_alloc_msi),
    700         DEVMETHOD(pcib_release_msi,     pcib_release_msi),
    701         DEVMETHOD(pcib_alloc_msix,      pcib_alloc_msix),
    702         DEVMETHOD(pcib_release_msix,    pcib_release_msix),
    703         DEVMETHOD(pcib_map_msi,         pcib_map_msi),
    704 
    705         DEVMETHOD_END
     709        DEVMETHOD(pcib_route_interrupt, legacy_pcib_route_interrupt),
     710
     711        {0, 0}
    706712};
    707713
    708714static devclass_t pcib_devclass;
    709715
    710 DEFINE_CLASS_0(pcib, pcibios_pcib_driver, pcibios_pcib_pci_methods,
    711     sizeof(struct pcib_softc));
     716DEFINE_CLASS_1(pcib, pcibios_pcib_driver, pcibios_pcib_pci_methods,
     717    sizeof(struct pcib_softc), pcib_driver);
    712718DRIVER_MODULE(pcibios_pcib, pci, pcibios_pcib_driver, pcib_devclass, 0, 0);
    713719
     
    728734        return (-2000);
    729735}
    730 
    731 static int
    732 pcibios_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
    733 {
    734         return (pci_pir_route_interrupt(pci_get_bus(dev), pci_get_slot(dev),
    735                 pci_get_function(dev), pin));
    736 }
    737 #endif /* __rtems__ */
     736#endif
  • freebsd/sys/sh/sh/legacy.c

    rce96623 r66659ff  
    5555#endif
    5656
     57#include <machine/clock.h>
    5758#include <machine/legacyvar.h>
    5859#include <machine/resource.h>
     
    352353        struct cpu_device *cpdev;
    353354
    354         if (index != CPU_IVAR_PCPU)
     355        switch (index) {
     356        case CPU_IVAR_PCPU:
     357                cpdev = device_get_ivars(child);
     358                *result = (uintptr_t)cpdev->cd_pcpu;
     359                break;
     360#ifndef __rtems__
     361        case CPU_IVAR_NOMINAL_MHZ:
     362                if (tsc_is_invariant) {
     363                        *result = (uintptr_t)(atomic_load_acq_64(&tsc_freq) /
     364                            1000000);
     365                        break;
     366                }
     367                /* FALLTHROUGH */
     368#endif /* __rtems__ */
     369        default:
    355370                return (ENOENT);
    356         cpdev = device_get_ivars(child);
    357         *result = (uintptr_t)cpdev->cd_pcpu;
     371        }
    358372        return (0);
    359373}
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