Changeset 64f4ac2 in rtems


Ignore:
Timestamp:
Feb 24, 2014, 9:48:13 AM (6 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
c5b1e20
Parents:
80186ca8
git-author:
Sebastian Huber <sebastian.huber@…> (02/24/14 09:48:13)
git-committer:
Sebastian Huber <sebastian.huber@…> (02/28/14 08:06:19)
Message:

bsp/leon3: Add new cache manager implementation

The previous implementation used an instruction cache line size of 0,
this is a bogus value. Use a instruction cache line size of 64 since
the L2 cache may have a line size of 32 or 64. A greater value should
cause no harm.

Use a FLUSH operation for _CPU_cache_invalidate_instruction_range().

This is a preperation step to support the L2 cache.

Location:
c/src/lib/libbsp/sparc/leon3
Files:
1 added
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/sparc/leon3/Makefile.am

    r80186ca8 r64f4ac2  
    118118libbsp_a_SOURCES += timer/timer.c
    119119
     120# Cache
     121libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
     122libbsp_a_SOURCES += include/cache_.h
     123libbsp_a_CPPFLAGS = -I$(srcdir)/include
     124
    120125if HAS_SMP
    121126libbsp_a_SOURCES += smp/getcpuid.c
     
    156161libbsp_a_LIBADD = \
    157162    ../../../libcpu/@RTEMS_CPU@/access.rel \
    158     ../../../libcpu/@RTEMS_CPU@/cache.rel \
    159163    ../../../libcpu/@RTEMS_CPU@/reg_win.rel \
    160164    ../../../libcpu/@RTEMS_CPU@/syscall.rel
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