Changeset 64f4ac2 in rtems

Timestamp:
02/24/14 09:48:13 (10 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, 5, master
Children:
c5b1e20
Parents:
80186ca8
git-author:
Sebastian Huber <sebastian.huber@…> (02/24/14 09:48:13)
git-committer:
Sebastian Huber <sebastian.huber@…> (02/28/14 08:06:19)
Message:

bsp/leon3: Add new cache manager implementation

The previous implementation used an instruction cache line size of 0,
this is a bogus value. Use a instruction cache line size of 64 since
the L2 cache may have a line size of 32 or 64. A greater value should
cause no harm.

Use a FLUSH operation for _CPU_cache_invalidate_instruction_range().

This is a preperation step to support the L2 cache.

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