Index: c/src/lib/libbsp/bfin/bf537Stamp/ChangeLog
===================================================================
--- c/src/lib/libbsp/bfin/bf537Stamp/ChangeLog	(revision 6ff3add12326dd7878946d726c4260e1ec9f3a3b)
+++ c/src/lib/libbsp/bfin/bf537Stamp/ChangeLog	(revision 64501892a93468ccd04048bb83b35dc8eeb43b95)
@@ -1,2 +1,9 @@
+2009-05-25	Allan Hessenflow <allanh@kallisti.com>
+
+	* startup/bspstart.c, startup/linkcmds: Enable caches and therefore
+	enable the mmu.
+	* start/start.S: Correct call to boot_card to meet bfin abi by
+	clearing l0 - l3 and allocating some stack space.
+
 2009-04-28	Chris Johns <chrisj@rtems.org>
 
Index: c/src/lib/libbsp/bfin/bf537Stamp/startup/bspstart.c
===================================================================
--- c/src/lib/libbsp/bfin/bf537Stamp/startup/bspstart.c	(revision 6ff3add12326dd7878946d726c4260e1ec9f3a3b)
+++ c/src/lib/libbsp/bfin/bf537Stamp/startup/bspstart.c	(revision 64501892a93468ccd04048bb83b35dc8eeb43b95)
@@ -20,13 +20,51 @@
 #include <bsp.h>
 #include <libcpu/bf537.h>
+#include <libcpu/ebiuRegs.h>
 #include <libcpu/gpioRegs.h>
 #include <libcpu/mmu.h>
+#include <libcpu/mmuRegs.h>
 #include <libcpu/interrupt.h>
 
 
-#if 0
-static bfin_mmu_region_t mmuRegions[] = {
+static bfin_mmu_config_t mmuRegions = {
+    /* instruction */
+    {
+        {(void *) 0x00000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0x00400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0x00800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0x00c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0x01000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0x01400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0x01800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0x01c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0x02000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0x02400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0x02800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0x02c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0x03000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0x20000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0xff800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_NOCACHE},
+        {(void *) 0xffc00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_NOCACHE}
+    },
+    /* data */
+    {
+        {(void *) 0x00000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0x00400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0x00800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0x00c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0x01000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0x01400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0x01800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0x01c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0x02000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0x02400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0x02800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0x02c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0x03000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0x20000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0xff800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_NOCACHE},
+        {(void *) 0xffc00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_NOCACHE}
+    }
 };
-#endif
 
 void Init_RTC(void);
@@ -53,5 +91,9 @@
   /* BSP Hardware Initialization*/
 
-  /*bfin_mmu_init(sizeof(mmuRegions) / sizeof(mmuRegions[0]), mmuRegions);*/
+  *(uint32_t volatile *) DMEM_CONTROL |= DMEM_CONTROL_PORT_PREF0;
+  *(uint32_t volatile *) DMEM_CONTROL &= ~DMEM_CONTROL_PORT_PREF1;
+  bfin_mmu_init(&mmuRegions);
+  rtems_cache_enable_instruction();
+  rtems_cache_enable_data();
 
   Init_RTC();   /* Blackfin Real Time Clock initialization */
@@ -97,4 +139,14 @@
 
 static void initEBIU(void) {
+
+  /* by default the processor has priority over dma channels for access to
+     external memory.  this has been seen to result in dma unerruns on
+     ethernet transmit; it seems likely it could cause dma overruns on
+     ethernet receive as well.  setting the following bit gives the dma
+     channels priority over the cpu, fixing that problem.  unfortunately
+     we don't have finer grain control than that; all dma channels now
+     have priority over the cpu. */
+  *(uint16_t volatile *) EBIU_AMGCTL |= EBIU_AMGCTL_CDPRIO;
+
 #ifdef BISON
   /* Configure FLASH */
Index: c/src/lib/libbsp/bfin/bf537Stamp/startup/linkcmds
===================================================================
--- c/src/lib/libbsp/bfin/bf537Stamp/startup/linkcmds	(revision 6ff3add12326dd7878946d726c4260e1ec9f3a3b)
+++ c/src/lib/libbsp/bfin/bf537Stamp/startup/linkcmds	(revision 64501892a93468ccd04048bb83b35dc8eeb43b95)
@@ -13,5 +13,9 @@
  */
 _RamBase = DEFINED(_RamBase) ? _RamBase : 0x0;
-_RamSize = DEFINED(_RamSize) ? _RamSize : 0x04000000;
+/* bf537stamp has 64MB ram, but dynamic mmu tables have not yet been
+   implemented.  there are not enough static entries to support 64MB
+   along with banks for io and flash, so waste some RAM at the end
+   to free up mmu entries. */
+_RamSize = DEFINED(_RamSize) ? _RamSize : 0x03400000;
 _HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0;
 _StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
