Changeset 64501892 in rtems


Ignore:
Timestamp:
May 27, 2009, 11:58:16 AM (10 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, master
Children:
31099c7d
Parents:
6ff3add
Message:

2009-05-25 Allan Hessenflow <allanh@…>

PR 1415/bsps

  • startup/bspstart.c, startup/linkcmds: Enable caches and therefore enable the mmu.
  • start/start.S: Correct call to boot_card to meet bfin abi by clearing l0 - l3 and allocating some stack space.
Location:
c/src/lib/libbsp/bfin/bf537Stamp
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/bfin/bf537Stamp/ChangeLog

    r6ff3add r64501892  
     12009-05-25      Allan Hessenflow <allanh@kallisti.com>
     2
     3        * startup/bspstart.c, startup/linkcmds: Enable caches and therefore
     4        enable the mmu.
     5        * start/start.S: Correct call to boot_card to meet bfin abi by
     6        clearing l0 - l3 and allocating some stack space.
     7
    182009-04-28      Chris Johns <chrisj@rtems.org>
    29
  • c/src/lib/libbsp/bfin/bf537Stamp/startup/bspstart.c

    r6ff3add r64501892  
    2020#include <bsp.h>
    2121#include <libcpu/bf537.h>
     22#include <libcpu/ebiuRegs.h>
    2223#include <libcpu/gpioRegs.h>
    2324#include <libcpu/mmu.h>
     25#include <libcpu/mmuRegs.h>
    2426#include <libcpu/interrupt.h>
    2527
    2628
    27 #if 0
    28 static bfin_mmu_region_t mmuRegions[] = {
     29static bfin_mmu_config_t mmuRegions = {
     30    /* instruction */
     31    {
     32        {(void *) 0x00000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
     33        {(void *) 0x00400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
     34        {(void *) 0x00800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
     35        {(void *) 0x00c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
     36        {(void *) 0x01000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
     37        {(void *) 0x01400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
     38        {(void *) 0x01800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
     39        {(void *) 0x01c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
     40        {(void *) 0x02000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
     41        {(void *) 0x02400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
     42        {(void *) 0x02800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
     43        {(void *) 0x02c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
     44        {(void *) 0x03000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
     45        {(void *) 0x20000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
     46        {(void *) 0xff800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_NOCACHE},
     47        {(void *) 0xffc00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_NOCACHE}
     48    },
     49    /* data */
     50    {
     51        {(void *) 0x00000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
     52        {(void *) 0x00400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
     53        {(void *) 0x00800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
     54        {(void *) 0x00c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
     55        {(void *) 0x01000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
     56        {(void *) 0x01400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
     57        {(void *) 0x01800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
     58        {(void *) 0x01c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
     59        {(void *) 0x02000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
     60        {(void *) 0x02400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
     61        {(void *) 0x02800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
     62        {(void *) 0x02c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
     63        {(void *) 0x03000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
     64        {(void *) 0x20000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
     65        {(void *) 0xff800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_NOCACHE},
     66        {(void *) 0xffc00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_NOCACHE}
     67    }
    2968};
    30 #endif
    3169
    3270void Init_RTC(void);
     
    5391  /* BSP Hardware Initialization*/
    5492
    55   /*bfin_mmu_init(sizeof(mmuRegions) / sizeof(mmuRegions[0]), mmuRegions);*/
     93  *(uint32_t volatile *) DMEM_CONTROL |= DMEM_CONTROL_PORT_PREF0;
     94  *(uint32_t volatile *) DMEM_CONTROL &= ~DMEM_CONTROL_PORT_PREF1;
     95  bfin_mmu_init(&mmuRegions);
     96  rtems_cache_enable_instruction();
     97  rtems_cache_enable_data();
    5698
    5799  Init_RTC();   /* Blackfin Real Time Clock initialization */
     
    97139
    98140static void initEBIU(void) {
     141
     142  /* by default the processor has priority over dma channels for access to
     143     external memory.  this has been seen to result in dma unerruns on
     144     ethernet transmit; it seems likely it could cause dma overruns on
     145     ethernet receive as well.  setting the following bit gives the dma
     146     channels priority over the cpu, fixing that problem.  unfortunately
     147     we don't have finer grain control than that; all dma channels now
     148     have priority over the cpu. */
     149  *(uint16_t volatile *) EBIU_AMGCTL |= EBIU_AMGCTL_CDPRIO;
     150
    99151#ifdef BISON
    100152  /* Configure FLASH */
  • c/src/lib/libbsp/bfin/bf537Stamp/startup/linkcmds

    r6ff3add r64501892  
    1313 */
    1414_RamBase = DEFINED(_RamBase) ? _RamBase : 0x0;
    15 _RamSize = DEFINED(_RamSize) ? _RamSize : 0x04000000;
     15/* bf537stamp has 64MB ram, but dynamic mmu tables have not yet been
     16   implemented.  there are not enough static entries to support 64MB
     17   along with banks for io and flash, so waste some RAM at the end
     18   to free up mmu entries. */
     19_RamSize = DEFINED(_RamSize) ? _RamSize : 0x03400000;
    1620_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0;
    1721_StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
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