Changeset 63e91fe6 in rtems


Ignore:
Timestamp:
Feb 26, 2015, 5:39:05 PM (4 years ago)
Author:
Martin Galvan <martin.galvan@…>
Branches:
4.11, master
Children:
991fdb33
Parents:
6357e14a
git-author:
Martin Galvan <martin.galvan@…> (02/26/15 17:39:05)
git-committer:
Sebastian Huber <sebastian.huber@…> (02/27/15 10:56:51)
Message:

ARM: Fix _ARMV4_Exception_fiq_default

In _ARMV4_Exception_fiq_default, set the F bit of the SPSR so that when
it gets loaded back to the CPSR in save_more_context it won't re-enable
the FIQs.

Tested on a TMS570LS3137.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/arm/armv4-exception-default.S

    r6357e14a r63e91fe6  
    100100        mov     r4, #7
    101101
     102        /*
     103         * Don't enable FIQs yet. Set the FIQ disable bit in the SPSR
     104         * (which we'll load into the CPSR in save_more_context).
     105         */
     106        mrs r2, spsr
     107        orr r2, #ARM_PSR_F
     108        msr spsr_c, r2
     109
    102110save_more_context:
    103111
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