Changeset 637df35 in rtems for cpukit/score/cpu/i960


Ignore:
Timestamp:
Jul 12, 1995, 7:47:25 PM (26 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
6cc85032
Parents:
68931b5
Message:

Ada95, gnat, go32

File:
1 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/i960/cpu.c

    r68931b5 r637df35  
    4848}
    4949
    50 /*  _CPU__ISR_Install_vector
     50/*PAGE
     51 *
     52 *  _CPU_ISR_install_raw_handler
     53 */
     54 
     55#define _Is_vector_caching_enabled( _prcb ) \
     56   ((_prcb)->control_tbl->icon & 0x2000)
     57
     58void _CPU_ISR_install_raw_handler(
     59  unsigned32  vector,
     60  proc_ptr    new_handler,
     61  proc_ptr   *old_handler
     62)
     63{
     64  i960ca_PRCB *prcb = _CPU_Table.Prcb;
     65  proc_ptr    *cached_intr_tbl = NULL;
     66
     67  /*  The i80960CA does not support vectors 0-7.  The first 9 entries
     68   *  in the Interrupt Table are used to manage pending interrupts.
     69   *  Thus vector 8, the first valid vector number, is actually in
     70   *  slot 9 in the table.
     71   */
     72
     73  *old_handler = prcb->intr_tbl[ vector + 1 ];
     74
     75  prcb->intr_tbl[ vector + 1 ] = new_handler;
     76
     77  if ( _Is_vector_caching_enabled( prcb ) )
     78    if ( (vector & 0xf) == 0x2 )       /* cacheable? */
     79      cached_intr_tbl[ vector >> 4 ] = new_handler;
     80}
     81
     82/*PAGE
     83 *
     84 *  _CPU__ISR_install_vector
    5185 *
    5286 *  Install the RTEMS vector wrapper in the CPU's interrupt table.
     
    6195 */
    6296
    63 #define _Is_vector_caching_enabled( _prcb ) \
    64    ((_prcb)->control_tbl->icon & 0x2000)
    65 
    6697void _CPU_ISR_install_vector(
    6798  unsigned32  vector,
     
    70101)
    71102{
    72   i960ca_PRCB *prcb = _CPU_Table.Prcb;
    73   proc_ptr    *cached_intr_tbl = NULL;
    74 
    75 /*  The i80960CA does not support vectors 0-7.  The first 9 entries
    76  *  in the Interrupt Table are used to manage pending interrupts.
    77  *  Thus vector 8, the first valid vector number, is actually in
    78  *  slot 9 in the table.
    79  */
     103  proc_ptr ignored;
    80104
    81105  *old_handler = _ISR_Vector_table[ vector ];
    82106
     107  _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
     108
    83109  _ISR_Vector_table[ vector ] = new_handler;
    84 
    85   prcb->intr_tbl[ vector + 1 ] = _ISR_Handler;
    86   if ( _Is_vector_caching_enabled( prcb ) )
    87     if ( (vector & 0xf) == 0x2 )       /* cacheable? */
    88       cached_intr_tbl[ vector >> 4 ] = _ISR_Handler;
    89110}
    90111
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