Changeset 637df35 in rtems for c/src/exec/score/cpu/i960

Timestamp:

07/12/95 19:47:25 (28 years ago)

Author:

Joel Sherrill <joel.sherrill@…>

Branches:

4.10, 4.11, 4.8, 4.9, 5, master

Children:

6cc85032

Parents:

68931b5

Message:

Ada95, gnat, go32

Location:

c/src/exec/score/cpu/i960

Files:

• cpu.c (modified) (3 diffs)
• cpu.h (modified) (1 diff)

c/src/exec/score/cpu/i960/cpu.c

@@ -48 +48 @@
 }
 
-/*  _CPU__ISR_Install_vector
+/*PAGE
+ *
+ *  _CPU_ISR_install_raw_handler
+ */
+ 
+#define _Is_vector_caching_enabled( _prcb ) \
+   ((_prcb)->control_tbl->icon & 0x2000)
+
+void _CPU_ISR_install_raw_handler(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+)
+{
+  i960ca_PRCB *prcb = _CPU_Table.Prcb;
+  proc_ptr    *cached_intr_tbl = NULL;
+
+  /*  The i80960CA does not support vectors 0-7.  The first 9 entries
+   *  in the Interrupt Table are used to manage pending interrupts.
+   *  Thus vector 8, the first valid vector number, is actually in
+   *  slot 9 in the table.
+   */
+
+  *old_handler = prcb->intr_tbl[ vector + 1 ];
+
+  prcb->intr_tbl[ vector + 1 ] = new_handler;
+
+  if ( _Is_vector_caching_enabled( prcb ) )
+    if ( (vector & 0xf) == 0x2 )       /* cacheable? */
+      cached_intr_tbl[ vector >> 4 ] = new_handler;
+}
+
+/*PAGE
+ *
+ *  _CPU__ISR_install_vector
  *
  *  Install the RTEMS vector wrapper in the CPU's interrupt table.
@@ -61 +95 @@
  */
 
-#define _Is_vector_caching_enabled( _prcb ) \
-   ((_prcb)->control_tbl->icon & 0x2000)
-
 void _CPU_ISR_install_vector(
   unsigned32  vector,
@@ -70 +101 @@
 )
 {
-  i960ca_PRCB *prcb = _CPU_Table.Prcb;
-  proc_ptr    *cached_intr_tbl = NULL;
-
-/*  The i80960CA does not support vectors 0-7.  The first 9 entries
- *  in the Interrupt Table are used to manage pending interrupts.
- *  Thus vector 8, the first valid vector number, is actually in
- *  slot 9 in the table.
- */
+  proc_ptr ignored;
 
   *old_handler = _ISR_Vector_table[ vector ];
 
+  _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
+
   _ISR_Vector_table[ vector ] = new_handler;
-
-  prcb->intr_tbl[ vector + 1 ] = _ISR_Handler;
-  if ( _Is_vector_caching_enabled( prcb ) )
-    if ( (vector & 0xf) == 0x2 )       /* cacheable? */
-      cached_intr_tbl[ vector >> 4 ] = _ISR_Handler;
 }
 

c/src/exec/score/cpu/i960/cpu.h

@@ -359 +359 @@
 
 /*
+ *  _CPU_ISR_install_raw_handler
+ *
+ *  This routine installs a "raw" interrupt handler directly into the 
+ *  processor's vector table.
+ */
+ 
+void _CPU_ISR_install_raw_handler(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+);
+
+/*
  *  _CPU_ISR_install_vector
  *