Changeset 637df35 in rtems


Ignore:
Timestamp:
Jul 12, 1995, 7:47:25 PM (25 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
6cc85032
Parents:
68931b5
Message:

Ada95, gnat, go32

Files:
28 added
36 edited

Legend:

Unmodified
Added
Removed
  • c/ACKNOWLEDGEMENTS

    r68931b5 r637df35  
    4545  support m68k family members based on the mc68000 core.
    4646
     47+ Bryce Cogswell (cogswell@cs.uoregon.edu) submitted the support for MS-DOS
     48  as a development environment as well as djgpp/go32 as a target environment.
     49
    4750Finally, the RTEMS project would like to thank those who have contributed
    4851to the other free software efforts which RTEMS utilizes.  The primary RTEMS
  • c/src/exec/libcsupport/src/newlibc.c

    r68931b5 r637df35  
    283283 */
    284284
    285 #ifndef RTEMS_UNIX
     285#if !defined(RTEMS_UNIX) && !defined(__GO32__)
    286286void _exit(int status)
    287287{
  • c/src/exec/sapi/headers/sptables.h

    r68931b5 r637df35  
    4343
    4444const char _RTEMS_version[] =
    45   "RTEMS RELEASE V3.2.0 (" CPU_NAME "/" RTEMS_MODEL_NAME ")";
     45  "RTEMS RELEASE V3.2.01 (" CPU_NAME "/" RTEMS_MODEL_NAME ")";
    4646
    4747
  • c/src/exec/sapi/include/rtems/sptables.h

    r68931b5 r637df35  
    4343
    4444const char _RTEMS_version[] =
    45   "RTEMS RELEASE V3.2.0 (" CPU_NAME "/" RTEMS_MODEL_NAME ")";
     45  "RTEMS RELEASE V3.2.01 (" CPU_NAME "/" RTEMS_MODEL_NAME ")";
    4646
    4747
  • c/src/exec/score/cpu/hppa1.1/cpu.c

    r68931b5 r637df35  
    109109}
    110110
    111 /*  _CPU_ISR_install_vector
     111/*PAGE
     112 *
     113 *  _CPU_ISR_install_raw_handler
     114 */
     115 
     116void _CPU_ISR_install_raw_handler(
     117  unsigned32  vector,
     118  proc_ptr    new_handler,
     119  proc_ptr   *old_handler
     120)
     121{
     122  /*
     123   *  This is unsupported.
     124   */
     125
     126  _CPU_Fatal_halt( 0xdeaddead );
     127}
     128
     129/*PAGE
     130 *
     131 *  _CPU_ISR_install_vector
    112132 *
    113133 *  This kernel routine installs the RTEMS handler for the
  • c/src/exec/score/cpu/hppa1.1/cpu.h

    r68931b5 r637df35  
    494494
    495495/*
     496 *  _CPU_ISR_install_raw_handler
     497 *
     498 *  This routine installs a "raw" interrupt handler directly into the
     499 *  processor's vector table.
     500 */
     501 
     502void _CPU_ISR_install_raw_handler(
     503  unsigned32  vector,
     504  proc_ptr    new_handler,
     505  proc_ptr   *old_handler
     506);
     507
     508/*
    496509 *  _CPU_ISR_install_vector
    497510 *
  • c/src/exec/score/cpu/i386/asm.h

    r68931b5 r637df35  
    4040 *  have to define these as appropriate.
    4141 */
     42
     43/*
     44 *  Go32 suffers the same bug as __REGISTER_PREFIX__
     45 */
     46 
     47#if __GO32__
     48#undef  __USER_LABEL_PREFIX__
     49#define __USER_LABEL_PREFIX__ _
     50#endif
    4251
    4352#ifndef __USER_LABEL_PREFIX__
  • c/src/exec/score/cpu/i386/cpu.c

    r68931b5 r637df35  
    6868}
    6969
    70 /*  _CPU_ISR_install_vector
     70/*PAGE
     71 *
     72 *  _CPU_ISR_install_raw_handler
     73 */
     74 
     75#if __GO32__
     76#include <cpu.h>
     77#include <go32.h>
     78#include <dpmi.h>
     79#endif /* __GO32__ */
     80
     81void _CPU_ISR_install_raw_handler(
     82  unsigned32  vector,
     83  proc_ptr    new_handler,
     84  proc_ptr   *old_handler
     85)
     86{
     87#if __GO32__
     88    _go32_dpmi_seginfo handler_info;
     89 
     90    *old_handler =  0;    /* XXX not supported */
     91
     92    handler_info.pm_offset = new_handler;
     93    handler_info.pm_selector = _go32_my_cs();
     94
     95    /* install the IDT entry */
     96    _go32_dpmi_set_protected_mode_interrupt_vector( vector, &handler_info );
     97#else
     98  i386_IDT_slot idt;
     99  unsigned32    handler;
     100
     101  *old_handler =  0;    /* XXX not supported */
     102
     103  handler = (unsigned32) new_handler;
     104
     105  /* build the IDT entry */
     106  idt.offset_0_15      = handler & 0xffff;
     107  idt.segment_selector = i386_get_cs();
     108  idt.reserved         = 0x00;
     109  idt.p_dpl            = 0x8e;         /* present, ISR */
     110  idt.offset_16_31     = handler >> 16;
     111
     112  /* install the IDT entry */
     113  i386_Install_idt(
     114    (unsigned32) &idt,
     115    _CPU_Table.interrupt_table_segment,
     116    (unsigned32) _CPU_Table.interrupt_table_offset + (8 * vector)
     117  );
     118#endif
     119}
     120
     121/*PAGE
     122 *
     123 *  _CPU_ISR_install_vector
    71124 *
    72125 *  This kernel routine installs the RTEMS handler for the
     
    96149)
    97150{
    98   i386_IDT_slot idt;
     151  proc_ptr      ignored;
    99152  unsigned32    unique_handler;
     153
     154  *old_handler = _ISR_Vector_table[ vector ];
    100155
    101156  /* calculate the unique entry point for this vector */
    102157  unique_handler = _Interrupt_Handler_entry( vector );
    103158
    104   /* build the IDT entry */
    105   idt.offset_0_15      = ((unsigned32) unique_handler) & 0xffff;
    106   idt.segment_selector = i386_get_cs();
    107   idt.reserved         = 0x00;
    108   idt.p_dpl            = 0x8e;         /* present, ISR */
    109   idt.offset_16_31     = ((unsigned32) unique_handler) >> 16;
     159  _CPU_ISR_install_raw_handler( vector, (void *)unique_handler, &ignored );
    110160
    111   /* install the IDT entry */
    112   i386_Install_idt(
    113     (unsigned32) &idt,
    114     _CPU_Table.interrupt_table_segment,
    115     (unsigned32) _CPU_Table.interrupt_table_offset + (8 * vector)
    116   );
    117 
    118   /* "portable" part */
    119   *old_handler = _ISR_Vector_table[ vector ];
    120161  _ISR_Vector_table[ vector ] = new_handler;
    121162}
  • c/src/exec/score/cpu/i386/cpu.h

    r68931b5 r637df35  
    310310
    311311/*
     312 *  _CPU_ISR_install_raw_handler
     313 *
     314 *  This routine installs a "raw" interrupt handler directly into the
     315 *  processor's vector table.
     316 */
     317 
     318void _CPU_ISR_install_raw_handler(
     319  unsigned32  vector,
     320  proc_ptr    new_handler,
     321  proc_ptr   *old_handler
     322);
     323
     324/*
    312325 *  _CPU_ISR_install_vector
    313326 *
  • c/src/exec/score/cpu/i386/cpu_asm.s

    r68931b5 r637df35  
    548548        iret                                # return to interrupted thread
    549549
     550/*
     551 *  GO32 does not require these segment related routines.
     552 */
     553
     554#ifndef __GO32__
    550555/*PAGE
    551556 *
     
    649654        movl    ecx,eax                # eax = ecx
    650655        ret
     656#endif /* __GO32__ */
    651657
    652658END_CODE
  • c/src/exec/score/cpu/i386/i386.h

    r68931b5 r637df35  
    3232#undef i386
    3333#endif
    34 #define i386
     34#define i386 1
    3535
    3636#ifdef REPLACE_THIS_WITH_THE_CPU_MODEL
  • c/src/exec/score/cpu/i960/cpu.c

    r68931b5 r637df35  
    4848}
    4949
    50 /*  _CPU__ISR_Install_vector
     50/*PAGE
     51 *
     52 *  _CPU_ISR_install_raw_handler
     53 */
     54 
     55#define _Is_vector_caching_enabled( _prcb ) \
     56   ((_prcb)->control_tbl->icon & 0x2000)
     57
     58void _CPU_ISR_install_raw_handler(
     59  unsigned32  vector,
     60  proc_ptr    new_handler,
     61  proc_ptr   *old_handler
     62)
     63{
     64  i960ca_PRCB *prcb = _CPU_Table.Prcb;
     65  proc_ptr    *cached_intr_tbl = NULL;
     66
     67  /*  The i80960CA does not support vectors 0-7.  The first 9 entries
     68   *  in the Interrupt Table are used to manage pending interrupts.
     69   *  Thus vector 8, the first valid vector number, is actually in
     70   *  slot 9 in the table.
     71   */
     72
     73  *old_handler = prcb->intr_tbl[ vector + 1 ];
     74
     75  prcb->intr_tbl[ vector + 1 ] = new_handler;
     76
     77  if ( _Is_vector_caching_enabled( prcb ) )
     78    if ( (vector & 0xf) == 0x2 )       /* cacheable? */
     79      cached_intr_tbl[ vector >> 4 ] = new_handler;
     80}
     81
     82/*PAGE
     83 *
     84 *  _CPU__ISR_install_vector
    5185 *
    5286 *  Install the RTEMS vector wrapper in the CPU's interrupt table.
     
    6195 */
    6296
    63 #define _Is_vector_caching_enabled( _prcb ) \
    64    ((_prcb)->control_tbl->icon & 0x2000)
    65 
    6697void _CPU_ISR_install_vector(
    6798  unsigned32  vector,
     
    70101)
    71102{
    72   i960ca_PRCB *prcb = _CPU_Table.Prcb;
    73   proc_ptr    *cached_intr_tbl = NULL;
    74 
    75 /*  The i80960CA does not support vectors 0-7.  The first 9 entries
    76  *  in the Interrupt Table are used to manage pending interrupts.
    77  *  Thus vector 8, the first valid vector number, is actually in
    78  *  slot 9 in the table.
    79  */
     103  proc_ptr ignored;
    80104
    81105  *old_handler = _ISR_Vector_table[ vector ];
    82106
     107  _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
     108
    83109  _ISR_Vector_table[ vector ] = new_handler;
    84 
    85   prcb->intr_tbl[ vector + 1 ] = _ISR_Handler;
    86   if ( _Is_vector_caching_enabled( prcb ) )
    87     if ( (vector & 0xf) == 0x2 )       /* cacheable? */
    88       cached_intr_tbl[ vector >> 4 ] = _ISR_Handler;
    89110}
    90111
  • c/src/exec/score/cpu/i960/cpu.h

    r68931b5 r637df35  
    359359
    360360/*
     361 *  _CPU_ISR_install_raw_handler
     362 *
     363 *  This routine installs a "raw" interrupt handler directly into the
     364 *  processor's vector table.
     365 */
     366 
     367void _CPU_ISR_install_raw_handler(
     368  unsigned32  vector,
     369  proc_ptr    new_handler,
     370  proc_ptr   *old_handler
     371);
     372
     373/*
    361374 *  _CPU_ISR_install_vector
    362375 *
  • c/src/exec/score/cpu/m68k/cpu.c

    r68931b5 r637df35  
    4141}
    4242
    43 /*  _CPU_ISR_install_vector
     43/*PAGE
     44 *
     45 *  _CPU_ISR_install_raw_handler
     46 */
     47 
     48void _CPU_ISR_install_raw_handler(
     49  unsigned32  vector,
     50  proc_ptr    new_handler,
     51  proc_ptr   *old_handler
     52)
     53{
     54  proc_ptr *interrupt_table = NULL;
     55
     56  m68k_get_vbr( interrupt_table );
     57
     58  *old_handler = interrupt_table[ vector ];
     59
     60  interrupt_table[ vector ] = new_handler;
     61}
     62
     63/*PAGE
     64 *
     65 *  _CPU_ISR_install_vector
    4466 *
    4567 *  This kernel routine installs the RTEMS handler for the
     
    5274 *
    5375 *  Output parameters:  NONE
    54  *
    55  *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
    56  *  On-Line Applications Research Corporation (OAR).
    57  *
    58  *  This material may be reproduced by or for the U.S. Government pursuant
    59  *  to the copyright license under the clause at DFARS 252.227-7013.  This
    60  *  notice must appear in all copies of this file and its derivatives.
    61  *
    62  *  $Id$
    6376 */
    6477
     
    6982)
    7083{
    71   proc_ptr *interrupt_table = NULL;
    72 
    73   m68k_get_vbr( interrupt_table );
     84  proc_ptr ignored;
    7485
    7586  *old_handler = _ISR_Vector_table[ vector ];
    7687
     88  _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
     89
    7790  _ISR_Vector_table[ vector ] = new_handler;
    78   interrupt_table[ vector ] = _ISR_Handler;
    7991}
    8092
     
    101113 */
    102114const unsigned char __log2table[256] = {
    103     0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3,
    104     4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
    105     5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
    106     5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
    107     6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
    108     6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
    109     6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
    110     6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
    111     7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
    112     7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
    113     7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
    114     7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
    115     7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
    116     7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
    117     7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
    118     7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
     115    0, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     116    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     117    5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     118    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     119    6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     120    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     121    5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     122    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     123    7, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     124    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     125    5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     126    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     127    6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     128    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     129    5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     130    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0
    119131};
    120132#endif
  • c/src/exec/score/cpu/m68k/cpu.h

    r68931b5 r637df35  
    329329    extern const unsigned char __log2table[256]; \
    330330    \
    331     (_output) = 0;  /* avoids warnings */ \
    332     asm         (  "move.w     %1,%0\n"\
    333      "\tandi.w     #0xff00,%0\n"\
    334      "\tjbne       0f\n"\
    335      "\tmoveq.l    #0,%0\n"\
    336      "\tmove.b     (%2,%1.w),%0\n"\
    337      "\tjbra       1f\n"\
    338      "0:\tmoveq.l    #8,%0\n"\
    339      "\tlsr.w      #8,%1\n"\
    340      "\tadd.b      (%2,%1.w),%0\n"\
    341      "1:"\
    342      : "=&d" ((_output)) \
    343      : "d" ((_value)), "ao" (__log2table) \
    344      : "cc" ) ; \
     331    asm     ( "   tst.b   %1\n"           /* check for bits in ls byte */ \
     332              "   beq.s   0f\n"           /* branch if no bits set */ \
     333              "   moveq.l #0,%0\n"        /* set up for bits 0..7 */ \
     334              "   andi.w  #0x00ff,%1\n"   /* clear ms byte for add inst */ \
     335              "   bra.s   1f\n"           /* go add */ \
     336              "0: moveq.l #8,%0\n"        /* set up for bits 8..15 */ \
     337              "   lsr.w   #8,%1\n"        /* shift ms byte to ls byte, */ \
     338                                          /*   filling ms byte with 0s */ \
     339              "1: add.b   (%2,%1.w),%0\n" /* add offset for bit pattern */ \
     340               : "=&d" ((_output)) \
     341               : "d" ((_value)), "ao" (__log2table) \
     342               : "cc" ) ; \
    345343  }
    346344
     
    386384
    387385/*
     386 *  _CPU_ISR_install_raw_handler
     387 *
     388 *  This routine installs a "raw" interrupt handler directly into the
     389 *  processor's vector table.
     390 */
     391 
     392void _CPU_ISR_install_raw_handler(
     393  unsigned32  vector,
     394  proc_ptr    new_handler,
     395  proc_ptr   *old_handler
     396);
     397
     398/*
    388399 *  _CPU_ISR_install_vector
    389400 *
  • c/src/exec/score/cpu/no_cpu/cpu.c

    r68931b5 r637df35  
    6262}
    6363
    64 /*  _CPU_ISR_install_vector
     64/*PAGE
     65 *
     66 *  _CPU_ISR_install_raw_handler
     67 */
     68 
     69void _CPU_ISR_install_raw_handler(
     70  unsigned32  vector,
     71  proc_ptr    new_handler,
     72  proc_ptr   *old_handler
     73)
     74{
     75  /*
     76   *  This is where we install the interrupt handler into the "raw" interrupt
     77   *  table used by the CPU to dispatch interrupt handlers.
     78   */
     79}
     80
     81/*PAGE
     82 *
     83 *  _CPU_ISR_install_vector
    6584 *
    6685 *  This kernel routine installs the RTEMS handler for the
     
    7594 *
    7695 */
    77 
    7896
    7997void _CPU_ISR_install_vector(
     
    90108    *  handler for this vector number.
    91109    */
     110
     111   _CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
    92112
    93113   /*
  • c/src/exec/score/cpu/no_cpu/cpu.h

    r68931b5 r637df35  
    700700  rtems_cpu_table  *cpu_table,
    701701  void      (*thread_dispatch)
     702);
     703
     704/*
     705 *  _CPU_ISR_install_raw_handler
     706 *
     707 *  This routine installs a "raw" interrupt handler directly into the
     708 *  processor's vector table.
     709 */
     710 
     711void _CPU_ISR_install_raw_handler(
     712  unsigned32  vector,
     713  proc_ptr    new_handler,
     714  proc_ptr   *old_handler
    702715);
    703716
  • c/src/exec/score/cpu/unix/cpu.c

    r68931b5 r637df35  
    1818
    1919#include <rtems/system.h>
    20 #include <rtems/fatal.h>
    2120#include <rtems/isr.h>
    22 #include <rtems/wkspace.h>
    23 /*
    24  *  In order to get the types and prototypes used in this file under
    25  *  Solaris 2.3, it is necessary to pull the following magic.
    26  */
    27 
    28 #if defined(solaris)
    29 #warning "Ignore the undefining __STDC__ warning"
    30 #undef __STDC__
    31 #define __STDC__ 0
    32 #undef  _POSIX_C_SOURCE
    33 #endif
    3421
    3522#include <stdio.h>
     
    3926#include <time.h>
    4027
    41 extern void           set_vector(proc_ptr, int, int);
    42 extern void           _Thread_Dispatch(void);
    43 
    44 extern unsigned32 _Thread_Dispatch_disable_level;
    45 extern unsigned32 _SYSTEM_ID;
    46 extern boolean    _Context_Switch_necessary;
    47 
    48 
    49 rtems_status_code signal_initialize(void);
    50 void         Stray_signal(int);
    51 void         signal_enable(unsigned32);
    52 void         signal_disable(unsigned32);
    53 void         interrupt_handler();
    54 
    55 sigset_t   UNIX_SIGNAL_MASK;
    56 jmp_buf    default_context;
     28#ifndef SA_RESTART
     29#define SA_RESTART 0
     30#endif
     31
     32void  _CPU_Signal_initialize(void);
     33void  _CPU_Stray_signal(int);
     34void  _CPU_ISR_Handler(int);
     35
     36sigset_t         _CPU_Signal_mask;
     37Context_Control  _CPU_Context_Default_with_ISRs_enabled;
     38Context_Control  _CPU_Context_Default_with_ISRs_disabled;
    5739
    5840/*
     
    6143
    6244int cpu_number;
     45
     46/*PAGE
     47 *
     48 *  _CPU_ISR_From_CPU_Init
     49 */
     50
     51void _CPU_ISR_From_CPU_Init()
     52{
     53  unsigned32        i;
     54  proc_ptr          old_handler;
     55
     56
     57  /*
     58   * Block all the signals except SIGTRAP for the debugger
     59   * and SIGABRT for fatal errors.
     60   */
     61
     62  _CPU_ISR_Enable(1);
     63
     64  (void) sigfillset(&_CPU_Signal_mask);
     65  (void) sigdelset(&_CPU_Signal_mask, SIGTRAP);
     66  (void) sigdelset(&_CPU_Signal_mask, SIGABRT);
     67  (void) sigdelset(&_CPU_Signal_mask, SIGIOT);
     68  (void) sigdelset(&_CPU_Signal_mask, SIGCONT);
     69
     70  sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, 0);
     71
     72  /*
     73   * Set the handler for all signals to be signal_handler
     74   * which will then vector out to the correct handler
     75   * for whichever signal actually happened. Initially
     76   * set the vectors to the stray signal handler.
     77   */
     78
     79  for (i = 0; i < CPU_INTERRUPT_NUMBER_OF_VECTORS; i++)
     80      (void)_CPU_ISR_install_vector(i, _CPU_Stray_signal, &old_handler);
     81
     82  _CPU_Signal_initialize();
     83}
     84
     85void _CPU_Signal_initialize( void )
     86{
     87  struct sigaction  act;
     88  sigset_t          mask;
     89
     90  /* mark them all active except for TraceTrap  and Abort */
     91
     92  sigfillset(&mask);
     93  sigdelset(&mask, SIGTRAP);
     94  sigdelset(&mask, SIGABRT);
     95  sigdelset(&mask, SIGIOT);
     96  sigdelset(&mask, SIGCONT);
     97  sigprocmask(SIG_UNBLOCK, &mask, 0);
     98
     99  act.sa_handler = _CPU_ISR_Handler;
     100  act.sa_mask = mask;
     101  act.sa_flags = SA_RESTART;
     102
     103  sigaction(SIGHUP, &act, 0);
     104  sigaction(SIGINT, &act, 0);
     105  sigaction(SIGQUIT, &act, 0);
     106  sigaction(SIGILL, &act, 0);
     107  sigaction(SIGEMT, &act, 0);
     108  sigaction(SIGFPE, &act, 0);
     109  sigaction(SIGKILL, &act, 0);
     110  sigaction(SIGBUS, &act, 0);
     111  sigaction(SIGSEGV, &act, 0);
     112  sigaction(SIGSYS, &act, 0);
     113  sigaction(SIGPIPE, &act, 0);
     114  sigaction(SIGALRM, &act, 0);
     115  sigaction(SIGTERM, &act, 0);
     116  sigaction(SIGUSR1, &act, 0);
     117  sigaction(SIGUSR2, &act, 0);
     118  sigaction(SIGCHLD, &act, 0);
     119  sigaction(SIGCLD, &act, 0);
     120  sigaction(SIGPWR, &act, 0);
     121  sigaction(SIGVTALRM, &act, 0);
     122  sigaction(SIGPROF, &act, 0);
     123  sigaction(SIGIO, &act, 0);
     124  sigaction(SIGWINCH, &act, 0);
     125  sigaction(SIGSTOP, &act, 0);
     126  sigaction(SIGTTIN, &act, 0);
     127  sigaction(SIGTTOU, &act, 0);
     128  sigaction(SIGURG, &act, 0);
     129/*
     130 *  XXX: Really should be on HPUX.
     131 */
     132
     133#if defined(hppa1_1)
     134    sigaction(SIGLOST, &act, 0);
     135#endif
     136
     137}
     138
     139/*PAGE
     140 *
     141 *  _CPU_Context_From_CPU_Init
     142 */
     143
     144void _CPU_Context_From_CPU_Init()
     145{
     146
     147#if defined(hppa1_1) && defined(RTEMS_UNIXLIB)
     148    /*
     149     * HACK - set the _SYSTEM_ID to 0x20c so that setjmp/longjmp
     150     * will handle the full 32 floating point registers.
     151     *
     152     *  NOTE:  Is this a bug in HPUX9?
     153     */
     154
     155    {
     156      extern unsigned32 _SYSTEM_ID;
     157
     158      _SYSTEM_ID = 0x20c;
     159    }
     160#endif
     161
     162  /*
     163   *  get default values to use in _CPU_Context_Initialize()
     164   */
     165
     166  _CPU_ISR_Set_level( 0 );
     167  setjmp( _CPU_Context_Default_with_ISRs_enabled.regs );
     168  sigprocmask(
     169    SIG_SETMASK,    /* ignored when second arg is NULL */
     170    0,
     171    &_CPU_Context_Default_with_ISRs_enabled.isr_level
     172  );
     173
     174  _CPU_ISR_Set_level( 1 );
     175  setjmp( _CPU_Context_Default_with_ISRs_disabled.regs );
     176  sigprocmask(
     177    SIG_SETMASK,    /* ignored when second arg is NULL */
     178    0,
     179    &_CPU_Context_Default_with_ISRs_disabled.isr_level
     180  );
     181
     182}
    63183
    64184/*  _CPU_Initialize
     
    77197)
    78198{
    79   unsigned32  i;
    80 
    81199  if ( cpu_table == NULL )
    82     rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED );
     200    _CPU_Fatal_halt( RTEMS_NOT_CONFIGURED );
    83201
    84202  /*
     
    106224  _CPU_Table = *cpu_table;
    107225
    108 #if defined(hppa1_1) && defined(RTEMS_UNIXLIB)
    109     /*
    110      * HACK - set the _SYSTEM_ID to 0x20c so that setjmp/longjmp
    111      * will handle the full 32 floating point registers.
    112      *
    113      *  NOTE:  Is this a bug in HPUX9?
    114      */
    115 
    116     _SYSTEM_ID = 0x20c;
    117 #endif
    118 
    119   /*
    120    *  get default values to use in _CPU_Context_Initialize()
    121    */
    122 
    123    setjmp(default_context);
    124 
    125   /*
    126    * Block all the signals except SIGTRAP for the debugger
    127    * and SIGABRT for fatal errors.
    128    */
    129 
    130   _CPU_ISR_Set_signal_level(1);
    131 
    132   sigfillset(&UNIX_SIGNAL_MASK);
    133   sigdelset(&UNIX_SIGNAL_MASK, SIGTRAP);
    134   sigdelset(&UNIX_SIGNAL_MASK, SIGABRT);
    135   sigdelset(&UNIX_SIGNAL_MASK, SIGIOT);
    136   sigdelset(&UNIX_SIGNAL_MASK, SIGCONT);
    137 
    138   sigprocmask(SIG_BLOCK, &UNIX_SIGNAL_MASK, 0);
    139 
    140   /*
    141    * Set the handler for all signals to be signal_handler
    142    * which will then vector out to the correct handler
    143    * for whichever signal actually happened. Initially
    144    * set the vectors to the stray signal handler.
    145    */
    146 
    147   for (i = 0; i < 32; i++)
    148       (void)set_vector(Stray_signal, i, 1);
    149 
    150   signal_initialize();
    151 }
    152 
    153 /*  _CPU_ISR_install_vector
     226  _CPU_ISR_From_CPU_Init();
     227
     228  _CPU_Context_From_CPU_Init();
     229
     230}
     231
     232/*PAGE
     233 *
     234 *  _CPU_ISR_install_raw_handler
     235 */
     236
     237void _CPU_ISR_install_raw_handler(
     238  unsigned32  vector,
     239  proc_ptr    new_handler,
     240  proc_ptr   *old_handler
     241)
     242{
     243  _CPU_Fatal_halt( 0xdeaddead );
     244}
     245
     246/*PAGE
     247 *
     248 *  _CPU_ISR_install_vector
    154249 *
    155250 *  This kernel routine installs the RTEMS handler for the
     
    182277   /*
    183278    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
    184     *  be used by the _ISR_Handler so the user gets control.
     279    *  be used by the _CPU_ISR_Handler so the user gets control.
    185280    */
    186281
     
    216311void _CPU_Internal_threads_Idle_thread_body( void )
    217312{
    218     while (1)
    219         pause();
    220 }
     313  while (1)
     314    pause();
     315}
     316
     317/*PAGE
     318 *
     319 *  _CPU_Context_Initialize
     320 */
    221321
    222322void _CPU_Context_Initialize(
     
    228328)
    229329{
    230     unsigned32  *addr;
    231     unsigned32   jmp_addr;
    232     unsigned32   _stack_low;   /* lowest "stack aligned" address */
    233     unsigned32   _stack_high;  /* highest "stack aligned" address */
    234     unsigned32   _the_size;
    235 
    236     jmp_addr = (unsigned32) _entry_point;
    237 
    238     /*
    239      *  On CPUs with stacks which grow down, we build the stack
    240      *  based on the _stack_high address.  On CPUs with stacks which
    241      *  grow up, we build the stack based on the _stack_low address. 
    242      */
    243 
    244     _stack_low = ((unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT);
    245     _stack_low &= ~(CPU_STACK_ALIGNMENT - 1);
    246 
    247     _stack_high = ((unsigned32)(_stack_base) + _size);
    248     _stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
    249 
    250     _the_size = _size & ~(CPU_STACK_ALIGNMENT - 1);
    251 
    252     /*
    253      * Slam our jmp_buf template into the context we are creating
    254      */
    255 
    256     memcpy(_the_context, default_context, sizeof(jmp_buf));
    257 
    258     addr = (unsigned32 *)_the_context;
     330  void        *source;
     331  unsigned32  *addr;
     332  unsigned32   jmp_addr;
     333  unsigned32   _stack_low;   /* lowest "stack aligned" address */
     334  unsigned32   _stack_high;  /* highest "stack aligned" address */
     335  unsigned32   _the_size;
     336
     337  jmp_addr = (unsigned32) _entry_point;
     338
     339  /*
     340   *  On CPUs with stacks which grow down, we build the stack
     341   *  based on the _stack_high address.  On CPUs with stacks which
     342   *  grow up, we build the stack based on the _stack_low address. 
     343   */
     344
     345  _stack_low = ((unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT);
     346  _stack_low &= ~(CPU_STACK_ALIGNMENT - 1);
     347
     348  _stack_high = ((unsigned32)(_stack_base) + _size);
     349  _stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
     350
     351  _the_size = _size & ~(CPU_STACK_ALIGNMENT - 1);
     352
     353  /*
     354   * Slam our jmp_buf template into the context we are creating
     355   */
     356
     357  if ( _new_level == 0 )
     358    source = _CPU_Context_Default_with_ISRs_enabled.regs;
     359  else
     360    source = _CPU_Context_Default_with_ISRs_disabled.regs;
     361     
     362  memcpy(_the_context, source, sizeof(jmp_buf));
     363
     364  addr = (unsigned32 *)_the_context;
    259365
    260366#if defined(hppa1_1)
    261     *(addr + RP_OFF) = jmp_addr;
    262     *(addr + SP_OFF) = (unsigned32)(_stack_low + CPU_FRAME_SIZE);
    263 
    264     /*
    265      * See if we are using shared libraries by checking
    266      * bit 30 in 24 off of newp. If bit 30 is set then
    267      * we are using shared libraries and the jump address
    268      * is at what 24 off of newp points to so shove that
    269      * into 24 off of newp instead.
    270      */
    271 
    272     if (jmp_addr & 0x40000000) {
    273        jmp_addr &= 0xfffffffc;
    274        *(addr + RP_OFF) = (unsigned32)*(unsigned32 *)jmp_addr;
    275     }
     367  *(addr + RP_OFF) = jmp_addr;
     368  *(addr + SP_OFF) = (unsigned32)(_stack_low + CPU_FRAME_SIZE);
     369
     370  /*
     371   * See if we are using shared libraries by checking
     372   * bit 30 in 24 off of newp. If bit 30 is set then
     373   * we are using shared libraries and the jump address
     374   * is at what 24 off of newp points to so shove that
     375   * into 24 off of newp instead.
     376   */
     377
     378  if (jmp_addr & 0x40000000) {
     379    jmp_addr &= 0xfffffffc;
     380     *(addr + RP_OFF) = (unsigned32)*(unsigned32 *)jmp_addr;
     381  }
    276382#elif defined(sparc)
    277383
    278     /*
    279      *  See /usr/include/sys/stack.h in Solaris 2.3 for a nice
    280      *  diagram of the stack.
    281      */
    282 
    283     asm ("ta  0x03");            /* flush registers */
    284 
    285     *(addr + RP_OFF) = jmp_addr + ADDR_ADJ_OFFSET;
    286     *(addr + SP_OFF) = (unsigned32)(_stack_high - CPU_FRAME_SIZE);
    287     *(addr + FP_OFF) = (unsigned32)(_stack_high);
     384  /*
     385   *  See /usr/include/sys/stack.h in Solaris 2.3 for a nice
     386   *  diagram of the stack.
     387   */
     388
     389  asm ("ta  0x03");            /* flush registers */
     390
     391  *(addr + RP_OFF) = jmp_addr + ADDR_ADJ_OFFSET;
     392  *(addr + SP_OFF) = (unsigned32)(_stack_high - CPU_FRAME_SIZE);
     393  *(addr + FP_OFF) = (unsigned32)(_stack_high);
    288394#else
    289395#error "UNKNOWN CPU!!!"
    290396#endif
    291397
    292     if (_new_level)
    293         _CPU_ISR_Set_signal_level(1);
    294     else
    295         _CPU_ISR_Set_signal_level(0);
    296 
    297 }
     398}
     399
     400/*PAGE
     401 *
     402 *  _CPU_Context_restore
     403 */
    298404
    299405void _CPU_Context_restore(
     
    301407)
    302408{
    303     longjmp(next->regs, 0);
    304 }
     409  sigprocmask( SIG_SETMASK, &next->isr_level, 0 );
     410  longjmp( next->regs, 0 );
     411}
     412
     413/*PAGE
     414 *
     415 *  _CPU_Context_switch
     416 */
    305417
    306418void _CPU_Context_switch(
     
    309421)
    310422{
    311     /*
    312      * Save the current context
    313      */
    314 
    315     if (setjmp(current->regs) == 0) {
    316 
    317        /*
    318         * Switch to the new context
    319         */
    320 
    321        longjmp(next->regs, 0);
    322     }
    323 }
     423  /*
     424   *  Switch levels in one operation
     425   */
     426
     427  sigprocmask( SIG_SETMASK, &next->isr_level, &current->isr_level );
     428
     429  if (setjmp(current->regs) == 0) {    /* Save the current context */
     430     longjmp(next->regs, 0);           /* Switch to the new context */
     431  }
     432}
     433 
     434/*PAGE
     435 *
     436 *  _CPU_Save_float_context
     437 */
    324438
    325439void _CPU_Save_float_context(
     
    329443}
    330444
     445/*PAGE
     446 *
     447 *  _CPU_Restore_float_context
     448 */
     449
    331450void _CPU_Restore_float_context(
    332451  Context_Control_fp *fp_context
     
    335454}
    336455
    337 void _CPU_ISR_Set_signal_level(unsigned32 level)
    338 {
    339     if (level)
    340         _CPU_Disable_signal();
    341     else
    342         _CPU_Enable_signal(0);
    343 }
    344 
    345 
    346 unsigned32 _CPU_Disable_signal(void)
    347 {
    348     sigset_t  old_mask;
    349     sigset_t  empty_mask;
    350 
    351     sigemptyset(&empty_mask);
    352     sigemptyset(&old_mask);
    353     sigprocmask(SIG_BLOCK, &UNIX_SIGNAL_MASK, &old_mask);
    354 
    355     if (memcmp((char *)&empty_mask, (char *)&old_mask, sizeof(sigset_t)) != 0)
    356         return 1;
    357 
    358     return 0;
    359 }
    360 
    361 
    362 void _CPU_Enable_signal(unsigned32 level)
    363 {
    364     if (level == 0)
    365         sigprocmask(SIG_UNBLOCK, &UNIX_SIGNAL_MASK, 0);
    366 }
    367 
    368 
    369 /*
    370  * Support for external and spurious interrupts on HPPA
    371  *
    372  *  TODO:
    373  *    delete interrupt.c etc.
    374  *    Count interrupts
    375  *    make sure interrupts disabled properly
    376  *    should handler check again for more interrupts before exit?
    377  *    How to enable interrupts from an interrupt handler?
    378  *    Make sure there is an entry for everything in ISR_Vector_Table
    379  */
    380 
    381 /*
    382  * Init the external interrupt scheme
    383  * called by bsp_start()
    384  */
    385 
    386 rtems_status_code
    387 signal_initialize(void)
    388 {
    389     struct sigaction act;
    390     sigset_t         mask;
    391 
    392     /* mark them all active except for TraceTrap  and Abort */
    393 
    394     sigfillset(&mask);
    395     sigdelset(&mask, SIGTRAP);
    396     sigdelset(&mask, SIGABRT);
    397     sigdelset(&mask, SIGIOT);
    398     sigdelset(&mask, SIGCONT);
    399     sigprocmask(SIG_UNBLOCK, &mask, 0);
    400 
    401     act.sa_handler = interrupt_handler;
    402     act.sa_mask = mask;
    403 #if defined(solaris)
    404     act.sa_flags = SA_RESTART;
    405 #else
    406     act.sa_flags = 0;
    407 #endif
    408 
    409     sigaction(SIGHUP, &act, 0);
    410     sigaction(SIGINT, &act, 0);
    411     sigaction(SIGQUIT, &act, 0);
    412     sigaction(SIGILL, &act, 0);
    413     sigaction(SIGEMT, &act, 0);
    414     sigaction(SIGFPE, &act, 0);
    415     sigaction(SIGKILL, &act, 0);
    416     sigaction(SIGBUS, &act, 0);
    417     sigaction(SIGSEGV, &act, 0);
    418     sigaction(SIGSYS, &act, 0);
    419     sigaction(SIGPIPE, &act, 0);
    420     sigaction(SIGALRM, &act, 0);
    421     sigaction(SIGTERM, &act, 0);
    422     sigaction(SIGUSR1, &act, 0);
    423     sigaction(SIGUSR2, &act, 0);
    424     sigaction(SIGCHLD, &act, 0);
    425     sigaction(SIGCLD, &act, 0);
    426     sigaction(SIGPWR, &act, 0);
    427     sigaction(SIGVTALRM, &act, 0);
    428     sigaction(SIGPROF, &act, 0);
    429     sigaction(SIGIO, &act, 0);
    430     sigaction(SIGWINCH, &act, 0);
    431     sigaction(SIGSTOP, &act, 0);
    432     sigaction(SIGTTIN, &act, 0);
    433     sigaction(SIGTTOU, &act, 0);
    434     sigaction(SIGURG, &act, 0);
    435 /*
    436  *  XXX: Really should be on HPUX.
    437  */
    438 
    439 #if defined(hppa1_1)
    440     sigaction(SIGLOST, &act, 0);
    441 #endif
    442 
    443     return RTEMS_SUCCESSFUL;
    444 }
    445 
    446 
    447 /*
    448  * External interrupt handler.
    449  * This is installed as cpu interrupt handler.
    450  * It vectors out to specific external interrupt handlers.
    451  */
    452 
    453 void
    454 interrupt_handler(int vector)
    455 {
    456     if (_ISR_Nest_level++ == 0) {
    457         /* switch to interrupt stack */
    458     }
    459 
    460     _Thread_Dispatch_disable_level++;
    461 
    462     if (_ISR_Vector_table[vector]) {
    463        _ISR_Vector_table[vector](vector);
    464     }
    465     else {
    466        Stray_signal(vector);
    467     }
    468 
    469     if (_ISR_Nest_level-- == 0) {
    470         /* switch back to original stack */
    471     }
    472 
    473     _Thread_Dispatch_disable_level--;
    474 
    475     if (_Thread_Dispatch_disable_level == 0 &&
    476         (_Context_Switch_necessary || _ISR_Signals_to_thread_executing)) {
    477         _CPU_Enable_signal(0);
    478         _Thread_Dispatch();
    479     }
    480 }
    481 
    482 
    483 void
    484 Stray_signal(int sig_num)
    485 {
    486     char buffer[ 80 ];   
    487 
    488     /*
    489      *  We avoid using the stdio section of the library.
    490      *  The following is generally safe.
    491      */
    492 
    493     write(
    494       2,
    495       buffer,
    496       sprintf( buffer, "Stray signal %d\n", sig_num )
    497     );
     456/*PAGE
     457 *
     458 *  _CPU_ISR_Disable_support
     459 */
     460
     461unsigned32 _CPU_ISR_Disable_support(void)
     462{
     463  sigset_t  old_mask;
     464  sigset_t  empty_mask;
     465
     466  sigemptyset(&empty_mask);
     467  sigemptyset(&old_mask);
     468  sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, &old_mask);
     469
     470  if (memcmp((char *)&empty_mask, (char *)&old_mask, sizeof(sigset_t)) != 0)
     471    return 1;
     472
     473  return 0;
     474}
     475
     476/*PAGE
     477 *
     478 *  _CPU_ISR_Enable
     479 */
     480
     481void _CPU_ISR_Enable(
     482  unsigned32 level
     483)
     484{
     485  if (level == 0)
     486    sigprocmask(SIG_UNBLOCK, &_CPU_Signal_mask, 0);
     487  else
     488    sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, 0);
     489}
     490
     491/*PAGE
     492 *
     493 *  _CPU_ISR_Handler
     494 *
     495 *  External interrupt handler.
     496 *  This is installed as a UNIX signal handler.
     497 *  It vectors out to specific user interrupt handlers.
     498 */
     499
     500void _CPU_ISR_Handler(int vector)
     501{
     502  extern void        _Thread_Dispatch(void);
     503  extern unsigned32  _Thread_Dispatch_disable_level;
     504  extern boolean     _Context_Switch_necessary;
     505
     506
     507  if (_ISR_Nest_level++ == 0) {
     508      /* switch to interrupt stack */
     509  }
     510
     511  _Thread_Dispatch_disable_level++;
     512
     513  if (_ISR_Vector_table[vector]) {
     514     _ISR_Vector_table[vector](vector);
     515  } else {
     516     _CPU_Stray_signal(vector);
     517  }
     518
     519  if (_ISR_Nest_level-- == 0) {
     520      /* switch back to original stack */
     521  }
     522
     523  _Thread_Dispatch_disable_level--;
     524
     525  if (_Thread_Dispatch_disable_level == 0 &&
     526      (_Context_Switch_necessary || _ISR_Signals_to_thread_executing)) {
     527      _CPU_ISR_Enable(0);
     528      _Thread_Dispatch();
     529  }
     530}
     531
     532/*PAGE
     533 *
     534 *  _CPU_Stray_signal
     535 */
     536
     537void _CPU_Stray_signal(int sig_num)
     538{
     539  char buffer[ 80 ];   
     540
     541  /*
     542   *  We avoid using the stdio section of the library.
     543   *  The following is generally safe.
     544   */
     545
     546  write(
     547    2,
     548    buffer,
     549    sprintf( buffer, "Stray signal %d\n", sig_num )
     550  );
    498551 
    499     /*
    500      * If it was a "fatal" signal, then exit here
    501      * If app code has installed a hander for one of these, then
    502      * we won't call Stray_signal, so this is ok.
    503      */
     552  /*
     553   * If it was a "fatal" signal, then exit here
     554   * If app code has installed a hander for one of these, then
     555   * we won't call _CPU_Stray_signal, so this is ok.
     556   */
    504557 
    505     switch (sig_num)
    506     {
    507         case SIGINT:
    508         case SIGHUP:
    509         case SIGQUIT:
    510         case SIGILL:
    511         case SIGEMT:
    512         case SIGKILL:
    513         case SIGBUS:
    514         case SIGSEGV:
    515         case SIGTERM:
    516             _CPU_Fatal_error(0x100 + sig_num);
    517     }
    518 }
    519 
    520 
    521 void
    522 _CPU_Fatal_error(unsigned32 error)
    523 {
    524     setitimer(ITIMER_REAL, 0, 0);
    525 
    526     _exit(error);
    527 }
    528 
    529 int
    530 _CPU_ffs(unsigned32 value)
    531 {
    532     int output;
    533 
    534     output = ffs(value);
    535     output = output - 1;
    536 
    537     return(output);
    538 }
     558  switch (sig_num) {
     559      case SIGINT:
     560      case SIGHUP:
     561      case SIGQUIT:
     562      case SIGILL:
     563      case SIGEMT:
     564      case SIGKILL:
     565      case SIGBUS:
     566      case SIGSEGV:
     567      case SIGTERM:
     568          _CPU_Fatal_error(0x100 + sig_num);
     569  }
     570}
     571
     572/*PAGE
     573 *
     574 *  _CPU_Fatal_error
     575 */
     576
     577void _CPU_Fatal_error(unsigned32 error)
     578{
     579  setitimer(ITIMER_REAL, 0, 0);
     580
     581  _exit(error);
     582}
     583
     584/*PAGE
     585 *
     586 *  _CPU_ffs
     587 */
     588
     589int _CPU_ffs(unsigned32 value)
     590{
     591  int output;
     592  extern int ffs( int );
     593
     594  output = ffs(value);
     595  output = output - 1;
     596
     597  return output;
     598}
  • c/src/exec/score/cpu/unix/cpu.h

    r68931b5 r637df35  
    2727#endif
    2828
    29 #include <setjmp.h>
    3029#include <rtems/unix.h>
    3130#ifndef ASM
    3231#include <rtems/unixtypes.h>
    3332#endif
     33
     34#if defined(solaris2)
     35#undef  _POSIX_C_SOURCE
     36#define _POSIX_C_SOURCE 3
     37#undef  __STRICT_ANSI__
     38#define __STRICT_ANSI__
     39#endif
     40
     41#if 0
     42
     43/*
     44 *  In order to get the types and prototypes used in this file under
     45 *  Solaris 2.3, it is necessary to pull the following magic.
     46 */
     47
     48#if defined(solaris2)
     49#warning "Ignore the undefining __STDC__ warning"
     50#undef __STDC__
     51#define __STDC__ 0
     52#undef  _POSIX_C_SOURCE
     53#endif
     54
     55#endif
     56
     57#include <setjmp.h>
     58#include <signal.h>
    3459
    3560/* conditional compilation parameters */
     
    398423
    399424typedef struct {
    400     jmp_buf   regs;
     425  jmp_buf   regs;
     426  sigset_t  isr_level;
     427  int       junk;
    401428} Context_Control;
    402429
     
    568595 */
    569596
     597extern unsigned32 _CPU_ISR_Disable_support(void);
     598
    570599#define _CPU_ISR_Disable( _level ) \
    571600    do { \
    572       (_level) = _CPU_Disable_signal(); \
     601      (_level) = _CPU_ISR_Disable_support(); \
    573602    } while ( 0 )
    574603
     
    579608 */
    580609
    581 #define _CPU_ISR_Enable( _level )  \
    582     do { \
    583       _CPU_Enable_signal( (_level) ); \
    584     } while ( 0 )
     610void _CPU_ISR_Enable(unsigned32 level);
    585611
    586612/*
     
    611637#define _CPU_ISR_Set_level( new_level ) \
    612638  { \
    613       if ( new_level ) \
    614           (void) _CPU_Disable_signal(); \
    615       else \
    616           _CPU_Enable_signal( 0 ); \
     639    if ( new_level == 0 ) _CPU_ISR_Enable( 0 ); \
     640    else                  _CPU_ISR_Enable( 1 ); \
    617641  }
    618642
     
    794818
    795819/*
     820 *  _CPU_ISR_install_raw_handler
     821 *
     822 *  This routine installs a "raw" interrupt handler directly into the
     823 *  processor's vector table.
     824 */
     825 
     826void _CPU_ISR_install_raw_handler(
     827  unsigned32  vector,
     828  proc_ptr    new_handler,
     829  proc_ptr   *old_handler
     830);
     831
     832/*
    796833 *  _CPU_ISR_install_vector
    797834 *
     
    873910
    874911void _CPU_ISR_Set_signal_level(
    875   unsigned32 level
    876 );
    877 
    878 unsigned32 _CPU_Disable_signal( void );
    879 
    880 void _CPU_Enable_signal(
    881912  unsigned32 level
    882913);
  • c/src/lib/libc/newlibc.c

    r68931b5 r637df35  
    283283 */
    284284
    285 #ifndef RTEMS_UNIX
     285#if !defined(RTEMS_UNIX) && !defined(__GO32__)
    286286void _exit(int status)
    287287{
  • c/src/lib/libmisc/monitor/mon-symbols.c

    r68931b5 r637df35  
    1717 */
    1818
     19#include <rtems.h>
    1920#include <stdio.h>
    2021#include <stdlib.h>
    2122#include <string.h>
    22 #include <rtems.h>
    2323
    2424#include "symbols.h"
  • c/src/libmisc/monitor/mon-symbols.c

    r68931b5 r637df35  
    1717 */
    1818
     19#include <rtems.h>
    1920#include <stdio.h>
    2021#include <stdlib.h>
    2122#include <string.h>
    22 #include <rtems.h>
    2323
    2424#include "symbols.h"
  • c/src/tests/mptests/mp12/init.c

    r68931b5 r637df35  
    3434#include "gvar.h"
    3535
    36 rtems_unsigned8 Partition_area[ 1024 ];
     36rtems_unsigned8 Partition_area[ 1024 ] CPU_STRUCTURE_ALIGNMENT;
    3737
    3838rtems_task Init(
  • c/src/tests/sptests/spsize/size.c

    r68931b5 r637df35  
    1414 *  $Id$
    1515 */
    16 
    17 #include <stdlib.h>
    1816
    1917#include <rtems/system.h>
     
    4745#include <rtems/wkspace.h>
    4846#include <rtems/mp.h>
     47
     48#include <stdlib.h>
    4949
    5050/* These are always defined by the executive.
  • cpukit/libcsupport/src/newlibc.c

    r68931b5 r637df35  
    283283 */
    284284
    285 #ifndef RTEMS_UNIX
     285#if !defined(RTEMS_UNIX) && !defined(__GO32__)
    286286void _exit(int status)
    287287{
  • cpukit/libmisc/monitor/mon-symbols.c

    r68931b5 r637df35  
    1717 */
    1818
     19#include <rtems.h>
    1920#include <stdio.h>
    2021#include <stdlib.h>
    2122#include <string.h>
    22 #include <rtems.h>
    2323
    2424#include "symbols.h"
  • cpukit/score/cpu/hppa1.1/cpu.c

    r68931b5 r637df35  
    109109}
    110110
    111 /*  _CPU_ISR_install_vector
     111/*PAGE
     112 *
     113 *  _CPU_ISR_install_raw_handler
     114 */
     115 
     116void _CPU_ISR_install_raw_handler(
     117  unsigned32  vector,
     118  proc_ptr    new_handler,
     119  proc_ptr   *old_handler
     120)
     121{
     122  /*
     123   *  This is unsupported.
     124   */
     125
     126  _CPU_Fatal_halt( 0xdeaddead );
     127}
     128
     129/*PAGE
     130 *
     131 *  _CPU_ISR_install_vector
    112132 *
    113133 *  This kernel routine installs the RTEMS handler for the
  • cpukit/score/cpu/i386/asm.h

    r68931b5 r637df35  
    4040 *  have to define these as appropriate.
    4141 */
     42
     43/*
     44 *  Go32 suffers the same bug as __REGISTER_PREFIX__
     45 */
     46 
     47#if __GO32__
     48#undef  __USER_LABEL_PREFIX__
     49#define __USER_LABEL_PREFIX__ _
     50#endif
    4251
    4352#ifndef __USER_LABEL_PREFIX__
  • cpukit/score/cpu/i386/cpu.c

    r68931b5 r637df35  
    6868}
    6969
    70 /*  _CPU_ISR_install_vector
     70/*PAGE
     71 *
     72 *  _CPU_ISR_install_raw_handler
     73 */
     74 
     75#if __GO32__
     76#include <cpu.h>
     77#include <go32.h>
     78#include <dpmi.h>
     79#endif /* __GO32__ */
     80
     81void _CPU_ISR_install_raw_handler(
     82  unsigned32  vector,
     83  proc_ptr    new_handler,
     84  proc_ptr   *old_handler
     85)
     86{
     87#if __GO32__
     88    _go32_dpmi_seginfo handler_info;
     89 
     90    *old_handler =  0;    /* XXX not supported */
     91
     92    handler_info.pm_offset = new_handler;
     93    handler_info.pm_selector = _go32_my_cs();
     94
     95    /* install the IDT entry */
     96    _go32_dpmi_set_protected_mode_interrupt_vector( vector, &handler_info );
     97#else
     98  i386_IDT_slot idt;
     99  unsigned32    handler;
     100
     101  *old_handler =  0;    /* XXX not supported */
     102
     103  handler = (unsigned32) new_handler;
     104
     105  /* build the IDT entry */
     106  idt.offset_0_15      = handler & 0xffff;
     107  idt.segment_selector = i386_get_cs();
     108  idt.reserved         = 0x00;
     109  idt.p_dpl            = 0x8e;         /* present, ISR */
     110  idt.offset_16_31     = handler >> 16;
     111
     112  /* install the IDT entry */
     113  i386_Install_idt(
     114    (unsigned32) &idt,
     115    _CPU_Table.interrupt_table_segment,
     116    (unsigned32) _CPU_Table.interrupt_table_offset + (8 * vector)
     117  );
     118#endif
     119}
     120
     121/*PAGE
     122 *
     123 *  _CPU_ISR_install_vector
    71124 *
    72125 *  This kernel routine installs the RTEMS handler for the
     
    96149)
    97150{
    98   i386_IDT_slot idt;
     151  proc_ptr      ignored;
    99152  unsigned32    unique_handler;
     153
     154  *old_handler = _ISR_Vector_table[ vector ];
    100155
    101156  /* calculate the unique entry point for this vector */
    102157  unique_handler = _Interrupt_Handler_entry( vector );
    103158
    104   /* build the IDT entry */
    105   idt.offset_0_15      = ((unsigned32) unique_handler) & 0xffff;
    106   idt.segment_selector = i386_get_cs();
    107   idt.reserved         = 0x00;
    108   idt.p_dpl            = 0x8e;         /* present, ISR */
    109   idt.offset_16_31     = ((unsigned32) unique_handler) >> 16;
     159  _CPU_ISR_install_raw_handler( vector, (void *)unique_handler, &ignored );
    110160
    111   /* install the IDT entry */
    112   i386_Install_idt(
    113     (unsigned32) &idt,
    114     _CPU_Table.interrupt_table_segment,
    115     (unsigned32) _CPU_Table.interrupt_table_offset + (8 * vector)
    116   );
    117 
    118   /* "portable" part */
    119   *old_handler = _ISR_Vector_table[ vector ];
    120161  _ISR_Vector_table[ vector ] = new_handler;
    121162}
  • cpukit/score/cpu/i386/rtems/asm.h

    r68931b5 r637df35  
    4040 *  have to define these as appropriate.
    4141 */
     42
     43/*
     44 *  Go32 suffers the same bug as __REGISTER_PREFIX__
     45 */
     46 
     47#if __GO32__
     48#undef  __USER_LABEL_PREFIX__
     49#define __USER_LABEL_PREFIX__ _
     50#endif
    4251
    4352#ifndef __USER_LABEL_PREFIX__
  • cpukit/score/cpu/i960/cpu.c

    r68931b5 r637df35  
    4848}
    4949
    50 /*  _CPU__ISR_Install_vector
     50/*PAGE
     51 *
     52 *  _CPU_ISR_install_raw_handler
     53 */
     54 
     55#define _Is_vector_caching_enabled( _prcb ) \
     56   ((_prcb)->control_tbl->icon & 0x2000)
     57
     58void _CPU_ISR_install_raw_handler(
     59  unsigned32  vector,
     60  proc_ptr    new_handler,
     61  proc_ptr   *old_handler
     62)
     63{
     64  i960ca_PRCB *prcb = _CPU_Table.Prcb;
     65  proc_ptr    *cached_intr_tbl = NULL;
     66
     67  /*  The i80960CA does not support vectors 0-7.  The first 9 entries
     68   *  in the Interrupt Table are used to manage pending interrupts.
     69   *  Thus vector 8, the first valid vector number, is actually in
     70   *  slot 9 in the table.
     71   */
     72
     73  *old_handler = prcb->intr_tbl[ vector + 1 ];
     74
     75  prcb->intr_tbl[ vector + 1 ] = new_handler;
     76
     77  if ( _Is_vector_caching_enabled( prcb ) )
     78    if ( (vector & 0xf) == 0x2 )       /* cacheable? */
     79      cached_intr_tbl[ vector >> 4 ] = new_handler;
     80}
     81
     82/*PAGE
     83 *
     84 *  _CPU__ISR_install_vector
    5185 *
    5286 *  Install the RTEMS vector wrapper in the CPU's interrupt table.
     
    6195 */
    6296
    63 #define _Is_vector_caching_enabled( _prcb ) \
    64    ((_prcb)->control_tbl->icon & 0x2000)
    65 
    6697void _CPU_ISR_install_vector(
    6798  unsigned32  vector,
     
    70101)
    71102{
    72   i960ca_PRCB *prcb = _CPU_Table.Prcb;
    73   proc_ptr    *cached_intr_tbl = NULL;
    74 
    75 /*  The i80960CA does not support vectors 0-7.  The first 9 entries
    76  *  in the Interrupt Table are used to manage pending interrupts.
    77  *  Thus vector 8, the first valid vector number, is actually in
    78  *  slot 9 in the table.
    79  */
     103  proc_ptr ignored;
    80104
    81105  *old_handler = _ISR_Vector_table[ vector ];
    82106
     107  _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
     108
    83109  _ISR_Vector_table[ vector ] = new_handler;
    84 
    85   prcb->intr_tbl[ vector + 1 ] = _ISR_Handler;
    86   if ( _Is_vector_caching_enabled( prcb ) )
    87     if ( (vector & 0xf) == 0x2 )       /* cacheable? */
    88       cached_intr_tbl[ vector >> 4 ] = _ISR_Handler;
    89110}
    90111
  • cpukit/score/cpu/m68k/cpu.c

    r68931b5 r637df35  
    4141}
    4242
    43 /*  _CPU_ISR_install_vector
     43/*PAGE
     44 *
     45 *  _CPU_ISR_install_raw_handler
     46 */
     47 
     48void _CPU_ISR_install_raw_handler(
     49  unsigned32  vector,
     50  proc_ptr    new_handler,
     51  proc_ptr   *old_handler
     52)
     53{
     54  proc_ptr *interrupt_table = NULL;
     55
     56  m68k_get_vbr( interrupt_table );
     57
     58  *old_handler = interrupt_table[ vector ];
     59
     60  interrupt_table[ vector ] = new_handler;
     61}
     62
     63/*PAGE
     64 *
     65 *  _CPU_ISR_install_vector
    4466 *
    4567 *  This kernel routine installs the RTEMS handler for the
     
    5274 *
    5375 *  Output parameters:  NONE
    54  *
    55  *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
    56  *  On-Line Applications Research Corporation (OAR).
    57  *
    58  *  This material may be reproduced by or for the U.S. Government pursuant
    59  *  to the copyright license under the clause at DFARS 252.227-7013.  This
    60  *  notice must appear in all copies of this file and its derivatives.
    61  *
    62  *  $Id$
    6376 */
    6477
     
    6982)
    7083{
    71   proc_ptr *interrupt_table = NULL;
    72 
    73   m68k_get_vbr( interrupt_table );
     84  proc_ptr ignored;
    7485
    7586  *old_handler = _ISR_Vector_table[ vector ];
    7687
     88  _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
     89
    7790  _ISR_Vector_table[ vector ] = new_handler;
    78   interrupt_table[ vector ] = _ISR_Handler;
    7991}
    8092
     
    101113 */
    102114const unsigned char __log2table[256] = {
    103     0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3,
    104     4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
    105     5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
    106     5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
    107     6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
    108     6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
    109     6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
    110     6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
    111     7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
    112     7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
    113     7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
    114     7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
    115     7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
    116     7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
    117     7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
    118     7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
     115    0, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     116    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     117    5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     118    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     119    6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     120    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     121    5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     122    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     123    7, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     124    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     125    5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     126    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     127    6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     128    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     129    5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
     130    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0
    119131};
    120132#endif
  • cpukit/score/cpu/no_cpu/cpu.c

    r68931b5 r637df35  
    6262}
    6363
    64 /*  _CPU_ISR_install_vector
     64/*PAGE
     65 *
     66 *  _CPU_ISR_install_raw_handler
     67 */
     68 
     69void _CPU_ISR_install_raw_handler(
     70  unsigned32  vector,
     71  proc_ptr    new_handler,
     72  proc_ptr   *old_handler
     73)
     74{
     75  /*
     76   *  This is where we install the interrupt handler into the "raw" interrupt
     77   *  table used by the CPU to dispatch interrupt handlers.
     78   */
     79}
     80
     81/*PAGE
     82 *
     83 *  _CPU_ISR_install_vector
    6584 *
    6685 *  This kernel routine installs the RTEMS handler for the
     
    7594 *
    7695 */
    77 
    7896
    7997void _CPU_ISR_install_vector(
     
    90108    *  handler for this vector number.
    91109    */
     110
     111   _CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
    92112
    93113   /*
  • cpukit/score/cpu/unix/cpu.c

    r68931b5 r637df35  
    1818
    1919#include <rtems/system.h>
    20 #include <rtems/fatal.h>
    2120#include <rtems/isr.h>
    22 #include <rtems/wkspace.h>
    23 /*
    24  *  In order to get the types and prototypes used in this file under
    25  *  Solaris 2.3, it is necessary to pull the following magic.
    26  */
    27 
    28 #if defined(solaris)
    29 #warning "Ignore the undefining __STDC__ warning"
    30 #undef __STDC__
    31 #define __STDC__ 0
    32 #undef  _POSIX_C_SOURCE
    33 #endif
    3421
    3522#include <stdio.h>
     
    3926#include <time.h>
    4027
    41 extern void           set_vector(proc_ptr, int, int);
    42 extern void           _Thread_Dispatch(void);
    43 
    44 extern unsigned32 _Thread_Dispatch_disable_level;
    45 extern unsigned32 _SYSTEM_ID;
    46 extern boolean    _Context_Switch_necessary;
    47 
    48 
    49 rtems_status_code signal_initialize(void);
    50 void         Stray_signal(int);
    51 void         signal_enable(unsigned32);
    52 void         signal_disable(unsigned32);
    53 void         interrupt_handler();
    54 
    55 sigset_t   UNIX_SIGNAL_MASK;
    56 jmp_buf    default_context;
     28#ifndef SA_RESTART
     29#define SA_RESTART 0
     30#endif
     31
     32void  _CPU_Signal_initialize(void);
     33void  _CPU_Stray_signal(int);
     34void  _CPU_ISR_Handler(int);
     35
     36sigset_t         _CPU_Signal_mask;
     37Context_Control  _CPU_Context_Default_with_ISRs_enabled;
     38Context_Control  _CPU_Context_Default_with_ISRs_disabled;
    5739
    5840/*
     
    6143
    6244int cpu_number;
     45
     46/*PAGE
     47 *
     48 *  _CPU_ISR_From_CPU_Init
     49 */
     50
     51void _CPU_ISR_From_CPU_Init()
     52{
     53  unsigned32        i;
     54  proc_ptr          old_handler;
     55
     56
     57  /*
     58   * Block all the signals except SIGTRAP for the debugger
     59   * and SIGABRT for fatal errors.
     60   */
     61
     62  _CPU_ISR_Enable(1);
     63
     64  (void) sigfillset(&_CPU_Signal_mask);
     65  (void) sigdelset(&_CPU_Signal_mask, SIGTRAP);
     66  (void) sigdelset(&_CPU_Signal_mask, SIGABRT);
     67  (void) sigdelset(&_CPU_Signal_mask, SIGIOT);
     68  (void) sigdelset(&_CPU_Signal_mask, SIGCONT);
     69
     70  sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, 0);
     71
     72  /*
     73   * Set the handler for all signals to be signal_handler
     74   * which will then vector out to the correct handler
     75   * for whichever signal actually happened. Initially
     76   * set the vectors to the stray signal handler.
     77   */
     78
     79  for (i = 0; i < CPU_INTERRUPT_NUMBER_OF_VECTORS; i++)
     80      (void)_CPU_ISR_install_vector(i, _CPU_Stray_signal, &old_handler);
     81
     82  _CPU_Signal_initialize();
     83}
     84
     85void _CPU_Signal_initialize( void )
     86{
     87  struct sigaction  act;
     88  sigset_t          mask;
     89
     90  /* mark them all active except for TraceTrap  and Abort */
     91
     92  sigfillset(&mask);
     93  sigdelset(&mask, SIGTRAP);
     94  sigdelset(&mask, SIGABRT);
     95  sigdelset(&mask, SIGIOT);
     96  sigdelset(&mask, SIGCONT);
     97  sigprocmask(SIG_UNBLOCK, &mask, 0);
     98
     99  act.sa_handler = _CPU_ISR_Handler;
     100  act.sa_mask = mask;
     101  act.sa_flags = SA_RESTART;
     102
     103  sigaction(SIGHUP, &act, 0);
     104  sigaction(SIGINT, &act, 0);
     105  sigaction(SIGQUIT, &act, 0);
     106  sigaction(SIGILL, &act, 0);
     107  sigaction(SIGEMT, &act, 0);
     108  sigaction(SIGFPE, &act, 0);
     109  sigaction(SIGKILL, &act, 0);
     110  sigaction(SIGBUS, &act, 0);
     111  sigaction(SIGSEGV, &act, 0);
     112  sigaction(SIGSYS, &act, 0);
     113  sigaction(SIGPIPE, &act, 0);
     114  sigaction(SIGALRM, &act, 0);
     115  sigaction(SIGTERM, &act, 0);
     116  sigaction(SIGUSR1, &act, 0);
     117  sigaction(SIGUSR2, &act, 0);
     118  sigaction(SIGCHLD, &act, 0);
     119  sigaction(SIGCLD, &act, 0);
     120  sigaction(SIGPWR, &act, 0);
     121  sigaction(SIGVTALRM, &act, 0);
     122  sigaction(SIGPROF, &act, 0);
     123  sigaction(SIGIO, &act, 0);
     124  sigaction(SIGWINCH, &act, 0);
     125  sigaction(SIGSTOP, &act, 0);
     126  sigaction(SIGTTIN, &act, 0);
     127  sigaction(SIGTTOU, &act, 0);
     128  sigaction(SIGURG, &act, 0);
     129/*
     130 *  XXX: Really should be on HPUX.
     131 */
     132
     133#if defined(hppa1_1)
     134    sigaction(SIGLOST, &act, 0);
     135#endif
     136
     137}
     138
     139/*PAGE
     140 *
     141 *  _CPU_Context_From_CPU_Init
     142 */
     143
     144void _CPU_Context_From_CPU_Init()
     145{
     146
     147#if defined(hppa1_1) && defined(RTEMS_UNIXLIB)
     148    /*
     149     * HACK - set the _SYSTEM_ID to 0x20c so that setjmp/longjmp
     150     * will handle the full 32 floating point registers.
     151     *
     152     *  NOTE:  Is this a bug in HPUX9?
     153     */
     154
     155    {
     156      extern unsigned32 _SYSTEM_ID;
     157
     158      _SYSTEM_ID = 0x20c;
     159    }
     160#endif
     161
     162  /*
     163   *  get default values to use in _CPU_Context_Initialize()
     164   */
     165
     166  _CPU_ISR_Set_level( 0 );
     167  setjmp( _CPU_Context_Default_with_ISRs_enabled.regs );
     168  sigprocmask(
     169    SIG_SETMASK,    /* ignored when second arg is NULL */
     170    0,
     171    &_CPU_Context_Default_with_ISRs_enabled.isr_level
     172  );
     173
     174  _CPU_ISR_Set_level( 1 );
     175  setjmp( _CPU_Context_Default_with_ISRs_disabled.regs );
     176  sigprocmask(
     177    SIG_SETMASK,    /* ignored when second arg is NULL */
     178    0,
     179    &_CPU_Context_Default_with_ISRs_disabled.isr_level
     180  );
     181
     182}
    63183
    64184/*  _CPU_Initialize
     
    77197)
    78198{
    79   unsigned32  i;
    80 
    81199  if ( cpu_table == NULL )
    82     rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED );
     200    _CPU_Fatal_halt( RTEMS_NOT_CONFIGURED );
    83201
    84202  /*
     
    106224  _CPU_Table = *cpu_table;
    107225
    108 #if defined(hppa1_1) && defined(RTEMS_UNIXLIB)
    109     /*
    110      * HACK - set the _SYSTEM_ID to 0x20c so that setjmp/longjmp
    111      * will handle the full 32 floating point registers.
    112      *
    113      *  NOTE:  Is this a bug in HPUX9?
    114      */
    115 
    116     _SYSTEM_ID = 0x20c;
    117 #endif
    118 
    119   /*
    120    *  get default values to use in _CPU_Context_Initialize()
    121    */
    122 
    123    setjmp(default_context);
    124 
    125   /*
    126    * Block all the signals except SIGTRAP for the debugger
    127    * and SIGABRT for fatal errors.
    128    */
    129 
    130   _CPU_ISR_Set_signal_level(1);
    131 
    132   sigfillset(&UNIX_SIGNAL_MASK);
    133   sigdelset(&UNIX_SIGNAL_MASK, SIGTRAP);
    134   sigdelset(&UNIX_SIGNAL_MASK, SIGABRT);
    135   sigdelset(&UNIX_SIGNAL_MASK, SIGIOT);
    136   sigdelset(&UNIX_SIGNAL_MASK, SIGCONT);
    137 
    138   sigprocmask(SIG_BLOCK, &UNIX_SIGNAL_MASK, 0);
    139 
    140   /*
    141    * Set the handler for all signals to be signal_handler
    142    * which will then vector out to the correct handler
    143    * for whichever signal actually happened. Initially
    144    * set the vectors to the stray signal handler.
    145    */
    146 
    147   for (i = 0; i < 32; i++)
    148       (void)set_vector(Stray_signal, i, 1);
    149 
    150   signal_initialize();
    151 }
    152 
    153 /*  _CPU_ISR_install_vector
     226  _CPU_ISR_From_CPU_Init();
     227
     228  _CPU_Context_From_CPU_Init();
     229
     230}
     231
     232/*PAGE
     233 *
     234 *  _CPU_ISR_install_raw_handler
     235 */
     236
     237void _CPU_ISR_install_raw_handler(
     238  unsigned32  vector,
     239  proc_ptr    new_handler,
     240  proc_ptr   *old_handler
     241)
     242{
     243  _CPU_Fatal_halt( 0xdeaddead );
     244}
     245
     246/*PAGE
     247 *
     248 *  _CPU_ISR_install_vector
    154249 *
    155250 *  This kernel routine installs the RTEMS handler for the
     
    182277   /*
    183278    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
    184     *  be used by the _ISR_Handler so the user gets control.
     279    *  be used by the _CPU_ISR_Handler so the user gets control.
    185280    */
    186281
     
    216311void _CPU_Internal_threads_Idle_thread_body( void )
    217312{
    218     while (1)
    219         pause();
    220 }
     313  while (1)
     314    pause();
     315}
     316
     317/*PAGE
     318 *
     319 *  _CPU_Context_Initialize
     320 */
    221321
    222322void _CPU_Context_Initialize(
     
    228328)
    229329{
    230     unsigned32  *addr;
    231     unsigned32   jmp_addr;
    232     unsigned32   _stack_low;   /* lowest "stack aligned" address */
    233     unsigned32   _stack_high;  /* highest "stack aligned" address */
    234     unsigned32   _the_size;
    235 
    236     jmp_addr = (unsigned32) _entry_point;
    237 
    238     /*
    239      *  On CPUs with stacks which grow down, we build the stack
    240      *  based on the _stack_high address.  On CPUs with stacks which
    241      *  grow up, we build the stack based on the _stack_low address. 
    242      */
    243 
    244     _stack_low = ((unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT);
    245     _stack_low &= ~(CPU_STACK_ALIGNMENT - 1);
    246 
    247     _stack_high = ((unsigned32)(_stack_base) + _size);
    248     _stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
    249 
    250     _the_size = _size & ~(CPU_STACK_ALIGNMENT - 1);
    251 
    252     /*
    253      * Slam our jmp_buf template into the context we are creating
    254      */
    255 
    256     memcpy(_the_context, default_context, sizeof(jmp_buf));
    257 
    258     addr = (unsigned32 *)_the_context;
     330  void        *source;
     331  unsigned32  *addr;
     332  unsigned32   jmp_addr;
     333  unsigned32   _stack_low;   /* lowest "stack aligned" address */
     334  unsigned32   _stack_high;  /* highest "stack aligned" address */
     335  unsigned32   _the_size;
     336
     337  jmp_addr = (unsigned32) _entry_point;
     338
     339  /*
     340   *  On CPUs with stacks which grow down, we build the stack
     341   *  based on the _stack_high address.  On CPUs with stacks which
     342   *  grow up, we build the stack based on the _stack_low address. 
     343   */
     344
     345  _stack_low = ((unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT);
     346  _stack_low &= ~(CPU_STACK_ALIGNMENT - 1);
     347
     348  _stack_high = ((unsigned32)(_stack_base) + _size);
     349  _stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
     350
     351  _the_size = _size & ~(CPU_STACK_ALIGNMENT - 1);
     352
     353  /*
     354   * Slam our jmp_buf template into the context we are creating
     355   */
     356
     357  if ( _new_level == 0 )
     358    source = _CPU_Context_Default_with_ISRs_enabled.regs;
     359  else
     360    source = _CPU_Context_Default_with_ISRs_disabled.regs;
     361     
     362  memcpy(_the_context, source, sizeof(jmp_buf));
     363
     364  addr = (unsigned32 *)_the_context;
    259365
    260366#if defined(hppa1_1)
    261     *(addr + RP_OFF) = jmp_addr;
    262     *(addr + SP_OFF) = (unsigned32)(_stack_low + CPU_FRAME_SIZE);
    263 
    264     /*
    265      * See if we are using shared libraries by checking
    266      * bit 30 in 24 off of newp. If bit 30 is set then
    267      * we are using shared libraries and the jump address
    268      * is at what 24 off of newp points to so shove that
    269      * into 24 off of newp instead.
    270      */
    271 
    272     if (jmp_addr & 0x40000000) {
    273        jmp_addr &= 0xfffffffc;
    274        *(addr + RP_OFF) = (unsigned32)*(unsigned32 *)jmp_addr;
    275     }
     367  *(addr + RP_OFF) = jmp_addr;
     368  *(addr + SP_OFF) = (unsigned32)(_stack_low + CPU_FRAME_SIZE);
     369
     370  /*
     371   * See if we are using shared libraries by checking
     372   * bit 30 in 24 off of newp. If bit 30 is set then
     373   * we are using shared libraries and the jump address
     374   * is at what 24 off of newp points to so shove that
     375   * into 24 off of newp instead.
     376   */
     377
     378  if (jmp_addr & 0x40000000) {
     379    jmp_addr &= 0xfffffffc;
     380     *(addr + RP_OFF) = (unsigned32)*(unsigned32 *)jmp_addr;
     381  }
    276382#elif defined(sparc)
    277383
    278     /*
    279      *  See /usr/include/sys/stack.h in Solaris 2.3 for a nice
    280      *  diagram of the stack.
    281      */
    282 
    283     asm ("ta  0x03");            /* flush registers */
    284 
    285     *(addr + RP_OFF) = jmp_addr + ADDR_ADJ_OFFSET;
    286     *(addr + SP_OFF) = (unsigned32)(_stack_high - CPU_FRAME_SIZE);
    287     *(addr + FP_OFF) = (unsigned32)(_stack_high);
     384  /*
     385   *  See /usr/include/sys/stack.h in Solaris 2.3 for a nice
     386   *  diagram of the stack.
     387   */
     388
     389  asm ("ta  0x03");            /* flush registers */
     390
     391  *(addr + RP_OFF) = jmp_addr + ADDR_ADJ_OFFSET;
     392  *(addr + SP_OFF) = (unsigned32)(_stack_high - CPU_FRAME_SIZE);
     393  *(addr + FP_OFF) = (unsigned32)(_stack_high);
    288394#else
    289395#error "UNKNOWN CPU!!!"
    290396#endif
    291397
    292     if (_new_level)
    293         _CPU_ISR_Set_signal_level(1);
    294     else
    295         _CPU_ISR_Set_signal_level(0);
    296 
    297 }
     398}
     399
     400/*PAGE
     401 *
     402 *  _CPU_Context_restore
     403 */
    298404
    299405void _CPU_Context_restore(
     
    301407)
    302408{
    303     longjmp(next->regs, 0);
    304 }
     409  sigprocmask( SIG_SETMASK, &next->isr_level, 0 );
     410  longjmp( next->regs, 0 );
     411}
     412
     413/*PAGE
     414 *
     415 *  _CPU_Context_switch
     416 */
    305417
    306418void _CPU_Context_switch(
     
    309421)
    310422{
    311     /*
    312      * Save the current context
    313      */
    314 
    315     if (setjmp(current->regs) == 0) {
    316 
    317        /*
    318         * Switch to the new context
    319         */
    320 
    321        longjmp(next->regs, 0);
    322     }
    323 }
     423  /*
     424   *  Switch levels in one operation
     425   */
     426
     427  sigprocmask( SIG_SETMASK, &next->isr_level, &current->isr_level );
     428
     429  if (setjmp(current->regs) == 0) {    /* Save the current context */
     430     longjmp(next->regs, 0);           /* Switch to the new context */
     431  }
     432}
     433 
     434/*PAGE
     435 *
     436 *  _CPU_Save_float_context
     437 */
    324438
    325439void _CPU_Save_float_context(
     
    329443}
    330444
     445/*PAGE
     446 *
     447 *  _CPU_Restore_float_context
     448 */
     449
    331450void _CPU_Restore_float_context(
    332451  Context_Control_fp *fp_context
     
    335454}
    336455
    337 void _CPU_ISR_Set_signal_level(unsigned32 level)
    338 {
    339     if (level)
    340         _CPU_Disable_signal();
    341     else
    342         _CPU_Enable_signal(0);
    343 }
    344 
    345 
    346 unsigned32 _CPU_Disable_signal(void)
    347 {
    348     sigset_t  old_mask;
    349     sigset_t  empty_mask;
    350 
    351     sigemptyset(&empty_mask);
    352     sigemptyset(&old_mask);
    353     sigprocmask(SIG_BLOCK, &UNIX_SIGNAL_MASK, &old_mask);
    354 
    355     if (memcmp((char *)&empty_mask, (char *)&old_mask, sizeof(sigset_t)) != 0)
    356         return 1;
    357 
    358     return 0;
    359 }
    360 
    361 
    362 void _CPU_Enable_signal(unsigned32 level)
    363 {
    364     if (level == 0)
    365         sigprocmask(SIG_UNBLOCK, &UNIX_SIGNAL_MASK, 0);
    366 }
    367 
    368 
    369 /*
    370  * Support for external and spurious interrupts on HPPA
    371  *
    372  *  TODO:
    373  *    delete interrupt.c etc.
    374  *    Count interrupts
    375  *    make sure interrupts disabled properly
    376  *    should handler check again for more interrupts before exit?
    377  *    How to enable interrupts from an interrupt handler?
    378  *    Make sure there is an entry for everything in ISR_Vector_Table
    379  */
    380 
    381 /*
    382  * Init the external interrupt scheme
    383  * called by bsp_start()
    384  */
    385 
    386 rtems_status_code
    387 signal_initialize(void)
    388 {
    389     struct sigaction act;
    390     sigset_t         mask;
    391 
    392     /* mark them all active except for TraceTrap  and Abort */
    393 
    394     sigfillset(&mask);
    395     sigdelset(&mask, SIGTRAP);
    396     sigdelset(&mask, SIGABRT);
    397     sigdelset(&mask, SIGIOT);
    398     sigdelset(&mask, SIGCONT);
    399     sigprocmask(SIG_UNBLOCK, &mask, 0);
    400 
    401     act.sa_handler = interrupt_handler;
    402     act.sa_mask = mask;
    403 #if defined(solaris)
    404     act.sa_flags = SA_RESTART;
    405 #else
    406     act.sa_flags = 0;
    407 #endif
    408 
    409     sigaction(SIGHUP, &act, 0);
    410     sigaction(SIGINT, &act, 0);
    411     sigaction(SIGQUIT, &act, 0);
    412     sigaction(SIGILL, &act, 0);
    413     sigaction(SIGEMT, &act, 0);
    414     sigaction(SIGFPE, &act, 0);
    415     sigaction(SIGKILL, &act, 0);
    416     sigaction(SIGBUS, &act, 0);
    417     sigaction(SIGSEGV, &act, 0);
    418     sigaction(SIGSYS, &act, 0);
    419     sigaction(SIGPIPE, &act, 0);
    420     sigaction(SIGALRM, &act, 0);
    421     sigaction(SIGTERM, &act, 0);
    422     sigaction(SIGUSR1, &act, 0);
    423     sigaction(SIGUSR2, &act, 0);
    424     sigaction(SIGCHLD, &act, 0);
    425     sigaction(SIGCLD, &act, 0);
    426     sigaction(SIGPWR, &act, 0);
    427     sigaction(SIGVTALRM, &act, 0);
    428     sigaction(SIGPROF, &act, 0);
    429     sigaction(SIGIO, &act, 0);
    430     sigaction(SIGWINCH, &act, 0);
    431     sigaction(SIGSTOP, &act, 0);
    432     sigaction(SIGTTIN, &act, 0);
    433     sigaction(SIGTTOU, &act, 0);
    434     sigaction(SIGURG, &act, 0);
    435 /*
    436  *  XXX: Really should be on HPUX.
    437  */
    438 
    439 #if defined(hppa1_1)
    440     sigaction(SIGLOST, &act, 0);
    441 #endif
    442 
    443     return RTEMS_SUCCESSFUL;
    444 }
    445 
    446 
    447 /*
    448  * External interrupt handler.
    449  * This is installed as cpu interrupt handler.
    450  * It vectors out to specific external interrupt handlers.
    451  */
    452 
    453 void
    454 interrupt_handler(int vector)
    455 {
    456     if (_ISR_Nest_level++ == 0) {
    457         /* switch to interrupt stack */
    458     }
    459 
    460     _Thread_Dispatch_disable_level++;
    461 
    462     if (_ISR_Vector_table[vector]) {
    463        _ISR_Vector_table[vector](vector);
    464     }
    465     else {
    466        Stray_signal(vector);
    467     }
    468 
    469     if (_ISR_Nest_level-- == 0) {
    470         /* switch back to original stack */
    471     }
    472 
    473     _Thread_Dispatch_disable_level--;
    474 
    475     if (_Thread_Dispatch_disable_level == 0 &&
    476         (_Context_Switch_necessary || _ISR_Signals_to_thread_executing)) {
    477         _CPU_Enable_signal(0);
    478         _Thread_Dispatch();
    479     }
    480 }
    481 
    482 
    483 void
    484 Stray_signal(int sig_num)
    485 {
    486     char buffer[ 80 ];   
    487 
    488     /*
    489      *  We avoid using the stdio section of the library.
    490      *  The following is generally safe.
    491      */
    492 
    493     write(
    494       2,
    495       buffer,
    496       sprintf( buffer, "Stray signal %d\n", sig_num )
    497     );
     456/*PAGE
     457 *
     458 *  _CPU_ISR_Disable_support
     459 */
     460
     461unsigned32 _CPU_ISR_Disable_support(void)
     462{
     463  sigset_t  old_mask;
     464  sigset_t  empty_mask;
     465
     466  sigemptyset(&empty_mask);
     467  sigemptyset(&old_mask);
     468  sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, &old_mask);
     469
     470  if (memcmp((char *)&empty_mask, (char *)&old_mask, sizeof(sigset_t)) != 0)
     471    return 1;
     472
     473  return 0;
     474}
     475
     476/*PAGE
     477 *
     478 *  _CPU_ISR_Enable
     479 */
     480
     481void _CPU_ISR_Enable(
     482  unsigned32 level
     483)
     484{
     485  if (level == 0)
     486    sigprocmask(SIG_UNBLOCK, &_CPU_Signal_mask, 0);
     487  else
     488    sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, 0);
     489}
     490
     491/*PAGE
     492 *
     493 *  _CPU_ISR_Handler
     494 *
     495 *  External interrupt handler.
     496 *  This is installed as a UNIX signal handler.
     497 *  It vectors out to specific user interrupt handlers.
     498 */
     499
     500void _CPU_ISR_Handler(int vector)
     501{
     502  extern void        _Thread_Dispatch(void);
     503  extern unsigned32  _Thread_Dispatch_disable_level;
     504  extern boolean     _Context_Switch_necessary;
     505
     506
     507  if (_ISR_Nest_level++ == 0) {
     508      /* switch to interrupt stack */
     509  }
     510
     511  _Thread_Dispatch_disable_level++;
     512
     513  if (_ISR_Vector_table[vector]) {
     514     _ISR_Vector_table[vector](vector);
     515  } else {
     516     _CPU_Stray_signal(vector);
     517  }
     518
     519  if (_ISR_Nest_level-- == 0) {
     520      /* switch back to original stack */
     521  }
     522
     523  _Thread_Dispatch_disable_level--;
     524
     525  if (_Thread_Dispatch_disable_level == 0 &&
     526      (_Context_Switch_necessary || _ISR_Signals_to_thread_executing)) {
     527      _CPU_ISR_Enable(0);
     528      _Thread_Dispatch();
     529  }
     530}
     531
     532/*PAGE
     533 *
     534 *  _CPU_Stray_signal
     535 */
     536
     537void _CPU_Stray_signal(int sig_num)
     538{
     539  char buffer[ 80 ];   
     540
     541  /*
     542   *  We avoid using the stdio section of the library.
     543   *  The following is generally safe.
     544   */
     545
     546  write(
     547    2,
     548    buffer,
     549    sprintf( buffer, "Stray signal %d\n", sig_num )
     550  );
    498551 
    499     /*
    500      * If it was a "fatal" signal, then exit here
    501      * If app code has installed a hander for one of these, then
    502      * we won't call Stray_signal, so this is ok.
    503      */
     552  /*
     553   * If it was a "fatal" signal, then exit here
     554   * If app code has installed a hander for one of these, then
     555   * we won't call _CPU_Stray_signal, so this is ok.
     556   */
    504557 
    505     switch (sig_num)
    506     {
    507         case SIGINT:
    508         case SIGHUP:
    509         case SIGQUIT:
    510         case SIGILL:
    511         case SIGEMT:
    512         case SIGKILL:
    513         case SIGBUS:
    514         case SIGSEGV:
    515         case SIGTERM:
    516             _CPU_Fatal_error(0x100 + sig_num);
    517     }
    518 }
    519 
    520 
    521 void
    522 _CPU_Fatal_error(unsigned32 error)
    523 {
    524     setitimer(ITIMER_REAL, 0, 0);
    525 
    526     _exit(error);
    527 }
    528 
    529 int
    530 _CPU_ffs(unsigned32 value)
    531 {
    532     int output;
    533 
    534     output = ffs(value);
    535     output = output - 1;
    536 
    537     return(output);
    538 }
     558  switch (sig_num) {
     559      case SIGINT:
     560      case SIGHUP:
     561      case SIGQUIT:
     562      case SIGILL:
     563      case SIGEMT:
     564      case SIGKILL:
     565      case SIGBUS:
     566      case SIGSEGV:
     567      case SIGTERM:
     568          _CPU_Fatal_error(0x100 + sig_num);
     569  }
     570}
     571
     572/*PAGE
     573 *
     574 *  _CPU_Fatal_error
     575 */
     576
     577void _CPU_Fatal_error(unsigned32 error)
     578{
     579  setitimer(ITIMER_REAL, 0, 0);
     580
     581  _exit(error);
     582}
     583
     584/*PAGE
     585 *
     586 *  _CPU_ffs
     587 */
     588
     589int _CPU_ffs(unsigned32 value)
     590{
     591  int output;
     592  extern int ffs( int );
     593
     594  output = ffs(value);
     595  output = output - 1;
     596
     597  return output;
     598}
  • testsuites/mptests/mp12/init.c

    r68931b5 r637df35  
    3434#include "gvar.h"
    3535
    36 rtems_unsigned8 Partition_area[ 1024 ];
     36rtems_unsigned8 Partition_area[ 1024 ] CPU_STRUCTURE_ALIGNMENT;
    3737
    3838rtems_task Init(
  • testsuites/sptests/spsize/size.c

    r68931b5 r637df35  
    1414 *  $Id$
    1515 */
    16 
    17 #include <stdlib.h>
    1816
    1917#include <rtems/system.h>
     
    4745#include <rtems/wkspace.h>
    4846#include <rtems/mp.h>
     47
     48#include <stdlib.h>
    4949
    5050/* These are always defined by the executive.
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