Index: c/src/exec/score/cpu/powerpc/rtems/score/ppc.h
===================================================================
--- c/src/exec/score/cpu/powerpc/rtems/score/ppc.h	(revision e4d7169f1c0d222c9f01e087b4867a846b2e4074)
+++ c/src/exec/score/cpu/powerpc/rtems/score/ppc.h	(revision 61bd030179f252d14f9639cf4921eb4eee07b5ef)
@@ -384,155 +384,4 @@
 #error "Undefined power of 2 for PPC_CACHE_ALIGNMENT"
 #endif
-
-#ifndef ASM
-
-/*
- * CACHE MANAGER: The following functions are CPU-specific.
- * They provide the basic implementation for the rtems_* cache
- * management routines. If a given function has no meaning for the CPU,
- * it does nothing by default.
- * 
- * FIXME: Some functions simply have not been implemented.
- */
- 
-#if defined(ppc603)			/* And possibly others */
-#define _CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
-#define _CPU_INST_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
-
-/* Helpful macros */
-#define PPC_Get_HID0( _value ) \
-  do { \
-      _value = 0;        /* to avoid warnings */ \
-      asm volatile( \
-          "mfspr %0, 0x3f0;"     /* get HID0 */ \
-          "isync" \
-          : "=r" (_value) \
-          : "0" (_value) \
-      ); \
-  } while (0)
-
-#define PPC_Set_HID0( _value ) \
-  do { \
-      asm volatile( \
-          "isync;" \
-          "mtspr 0x3f0, %0;"     /* load HID0 */ \
-          "isync" \
-          : "=r" (_value) \
-          : "0" (_value) \
-      ); \
-  } while (0)
-
-static inline void _CPU_enable_data_cache (
-	void )
-{
-  unsigned32 value;
-  PPC_Get_HID0( value );
-  value |= 0x00004000;        /* set DCE bit */
-  PPC_Set_HID0( value );
-}
-
-static inline void _CPU_disable_data_cache (
-	void )
-{
-  unsigned32 value;
-  PPC_Get_HID0( value );
-  value &= 0xFFFFBFFF;        /* clear DCE bit */
-  PPC_Set_HID0( value );
-}
-
-static inline void _CPU_enable_inst_cache (
-	void )
-{
-  unsigned32 value;
-  PPC_Get_HID0( value );
-  value |= 0x00008000;       /* Set ICE bit */
-  PPC_Set_HID0( value );
-}
-
-static inline void _CPU_disable_inst_cache (
-	void )
-{
-  unsigned32 value;
-  PPC_Get_HID0( value );
-  value &= 0xFFFF7FFF;       /* Clear ICE bit */
-  PPC_Set_HID0( value );
-}
-
-#elif ( defined(mpc860) || defined(mpc821) )
-
-#define _CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
-#define _CPU_INST_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
-
-#define mtspr(_spr,_reg)   __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) )
-#define isync   __asm__ volatile ("isync\n"::)
-
-static inline void _CPU_flush_1_data_cache_line(
-	const void * _address )
-{
-  register const void *__address = _address;
-  asm volatile ( "dcbf 0,%0" :: "r" (__address) );
-}
-
-static inline void _CPU_invalidate_1_data_cache_line(
-	const void * _address )
-{
-  register const void *__address = _address;
-  asm volatile ( "dcbi 0,%0" :: "r" (__address) );
-}
-
-static inline void _CPU_flush_entire_data_cache ( void ) {}
-static inline void _CPU_invalidate_entire_data_cache ( void ) {}
-static inline void _CPU_freeze_data_cache ( void ) {}
-static inline void _CPU_unfreeze_data_cache ( void ) {}
-
-static inline void _CPU_enable_data_cache (
-	void )
-{
-  unsigned32 r1;
-  r1 = (0x2<<24);
-  mtspr( 568, r1 );
-  isync;
-}
-
-static inline void _CPU_disable_data_cache (
-	void )
-{
-  unsigned32 r1;
-  r1 = (0x4<<24);
-  mtspr( 568, r1 );
-  isync;
-}
-
-static inline void _CPU_invalidate_1_inst_cache_line(
-	const void * _address )
-{
-  register const void *__address = _address;
-  asm volatile ( "icbi 0,%0" :: "r" (__address) );
-}
-
-static inline void _CPU_invalidate_entire_inst_cache ( void ) {}
-static inline void _CPU_freeze_inst_cache ( void ) {}
-static inline void _CPU_unfreeze_inst_cache ( void ) {}
-
-static inline void _CPU_enable_inst_cache (
-	void )
-{
-  unsigned32 r1;
-  r1 = (0x2<<24);
-  mtspr( 560, r1 );
-  isync;
-}
-
-static inline void _CPU_disable_inst_cache (
-	void )
-{
-  unsigned32 r1;
-  r1 = (0x4<<24);
-  mtspr( 560, r1 );
-  isync;
-}
-#endif
-
-#endif  /* !ASM */
 
 /*
Index: c/src/exec/score/cpu/powerpc/shared/ppc.h
===================================================================
--- c/src/exec/score/cpu/powerpc/shared/ppc.h	(revision e4d7169f1c0d222c9f01e087b4867a846b2e4074)
+++ c/src/exec/score/cpu/powerpc/shared/ppc.h	(revision 61bd030179f252d14f9639cf4921eb4eee07b5ef)
@@ -384,155 +384,4 @@
 #error "Undefined power of 2 for PPC_CACHE_ALIGNMENT"
 #endif
-
-#ifndef ASM
-
-/*
- * CACHE MANAGER: The following functions are CPU-specific.
- * They provide the basic implementation for the rtems_* cache
- * management routines. If a given function has no meaning for the CPU,
- * it does nothing by default.
- * 
- * FIXME: Some functions simply have not been implemented.
- */
- 
-#if defined(ppc603)			/* And possibly others */
-#define _CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
-#define _CPU_INST_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
-
-/* Helpful macros */
-#define PPC_Get_HID0( _value ) \
-  do { \
-      _value = 0;        /* to avoid warnings */ \
-      asm volatile( \
-          "mfspr %0, 0x3f0;"     /* get HID0 */ \
-          "isync" \
-          : "=r" (_value) \
-          : "0" (_value) \
-      ); \
-  } while (0)
-
-#define PPC_Set_HID0( _value ) \
-  do { \
-      asm volatile( \
-          "isync;" \
-          "mtspr 0x3f0, %0;"     /* load HID0 */ \
-          "isync" \
-          : "=r" (_value) \
-          : "0" (_value) \
-      ); \
-  } while (0)
-
-static inline void _CPU_enable_data_cache (
-	void )
-{
-  unsigned32 value;
-  PPC_Get_HID0( value );
-  value |= 0x00004000;        /* set DCE bit */
-  PPC_Set_HID0( value );
-}
-
-static inline void _CPU_disable_data_cache (
-	void )
-{
-  unsigned32 value;
-  PPC_Get_HID0( value );
-  value &= 0xFFFFBFFF;        /* clear DCE bit */
-  PPC_Set_HID0( value );
-}
-
-static inline void _CPU_enable_inst_cache (
-	void )
-{
-  unsigned32 value;
-  PPC_Get_HID0( value );
-  value |= 0x00008000;       /* Set ICE bit */
-  PPC_Set_HID0( value );
-}
-
-static inline void _CPU_disable_inst_cache (
-	void )
-{
-  unsigned32 value;
-  PPC_Get_HID0( value );
-  value &= 0xFFFF7FFF;       /* Clear ICE bit */
-  PPC_Set_HID0( value );
-}
-
-#elif ( defined(mpc860) || defined(mpc821) )
-
-#define _CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
-#define _CPU_INST_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
-
-#define mtspr(_spr,_reg)   __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) )
-#define isync   __asm__ volatile ("isync\n"::)
-
-static inline void _CPU_flush_1_data_cache_line(
-	const void * _address )
-{
-  register const void *__address = _address;
-  asm volatile ( "dcbf 0,%0" :: "r" (__address) );
-}
-
-static inline void _CPU_invalidate_1_data_cache_line(
-	const void * _address )
-{
-  register const void *__address = _address;
-  asm volatile ( "dcbi 0,%0" :: "r" (__address) );
-}
-
-static inline void _CPU_flush_entire_data_cache ( void ) {}
-static inline void _CPU_invalidate_entire_data_cache ( void ) {}
-static inline void _CPU_freeze_data_cache ( void ) {}
-static inline void _CPU_unfreeze_data_cache ( void ) {}
-
-static inline void _CPU_enable_data_cache (
-	void )
-{
-  unsigned32 r1;
-  r1 = (0x2<<24);
-  mtspr( 568, r1 );
-  isync;
-}
-
-static inline void _CPU_disable_data_cache (
-	void )
-{
-  unsigned32 r1;
-  r1 = (0x4<<24);
-  mtspr( 568, r1 );
-  isync;
-}
-
-static inline void _CPU_invalidate_1_inst_cache_line(
-	const void * _address )
-{
-  register const void *__address = _address;
-  asm volatile ( "icbi 0,%0" :: "r" (__address) );
-}
-
-static inline void _CPU_invalidate_entire_inst_cache ( void ) {}
-static inline void _CPU_freeze_inst_cache ( void ) {}
-static inline void _CPU_unfreeze_inst_cache ( void ) {}
-
-static inline void _CPU_enable_inst_cache (
-	void )
-{
-  unsigned32 r1;
-  r1 = (0x2<<24);
-  mtspr( 560, r1 );
-  isync;
-}
-
-static inline void _CPU_disable_inst_cache (
-	void )
-{
-  unsigned32 r1;
-  r1 = (0x4<<24);
-  mtspr( 560, r1 );
-  isync;
-}
-#endif
-
-#endif  /* !ASM */
 
 /*
Index: c/src/lib/libcpu/powerpc/configure.in
===================================================================
--- c/src/lib/libcpu/powerpc/configure.in	(revision e4d7169f1c0d222c9f01e087b4867a846b2e4074)
+++ c/src/lib/libcpu/powerpc/configure.in	(revision 61bd030179f252d14f9639cf4921eb4eee07b5ef)
@@ -71,3 +71,5 @@
 mpc6xx/wrapup/Makefile
 shared/Makefile
+shared/include/Makefile
+shared/src/Makefile
 wrapup/Makefile)
Index: c/src/lib/libcpu/powerpc/mpc8xx/clock/clock.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/clock/clock.c	(revision e4d7169f1c0d222c9f01e087b4867a846b2e4074)
+++ c/src/lib/libcpu/powerpc/mpc8xx/clock/clock.c	(revision 61bd030179f252d14f9639cf4921eb4eee07b5ef)
@@ -37,5 +37,5 @@
  */
 
-#include <bsp.h>
+#include <rtems.h>
 #include <clockdrv.h>
 #include <rtems/libio.h>
@@ -43,6 +43,4 @@
 #include <stdlib.h>                     /* for atexit() */
 #include <mpc8xx.h>
-
-extern rtems_cpu_table           Cpu_table;             /* owned by BSP */
 
 volatile rtems_unsigned32 Clock_driver_ticks;
@@ -79,35 +77,33 @@
   Clock_driver_ticks = 0;
   
-  pit_value = (BSP_Configuration.microseconds_per_tick *
-               Cpu_table.clicks_per_usec) - 1 ;
+  pit_value = (rtems_configuration_get_microseconds_per_tick() *
+               rtems_cpu_configuration_get_clicks_per_usec()) - 1 ;
   
   if (pit_value > 0xffff) {           /* pit is only 16 bits long */
     rtems_fatal_error_occurred(-1);
   }  
-  if (BSP_Configuration.ticks_per_timeslice) {
-    
-    /*
-     * initialize the interval here
-     * First tick is set to right amount of time in the future
-     * Future ticks will be incremented over last value set
-     * in order to provide consistent clicks in the face of
-     * interrupt overhead
-     */
-    
-    rtems_interrupt_catch(clock_isr, PPC_IRQ_LVL0, &previous_isr);
-    
-    m8xx.sccr &= ~(1<<24);
-    m8xx.pitc = pit_value;
-    
-    /* set PIT irq level, enable PIT, PIT interrupts */
-    /*  and clear int. status */
-    m8xx.piscr = M8xx_PISCR_PIRQ(0) |
-      M8xx_PISCR_PTE | M8xx_PISCR_PS | M8xx_PISCR_PIE; 
+
+  /*
+   * initialize the interval here
+   * First tick is set to right amount of time in the future
+   * Future ticks will be incremented over last value set
+   * in order to provide consistent clicks in the face of
+   * interrupt overhead
+   */
+  
+  rtems_interrupt_catch(clock_isr, PPC_IRQ_LVL0, &previous_isr);
+  
+  m8xx.sccr &= ~(1<<24);
+  m8xx.pitc = pit_value;
+  
+  /* set PIT irq level, enable PIT, PIT interrupts */
+  /*  and clear int. status */
+  m8xx.piscr = M8xx_PISCR_PIRQ(0) |
+    M8xx_PISCR_PTE | M8xx_PISCR_PS | M8xx_PISCR_PIE; 
     
 #ifdef EPPCBUG_SMC1
-    simask_copy = m8xx.simask | M8xx_SIMASK_LVM0;
+  simask_copy = m8xx.simask | M8xx_SIMASK_LVM0;
 #endif /* EPPCBUG_SMC1 */
-    m8xx.simask |= M8xx_SIMASK_LVM0;
-  }
+  m8xx.simask |= M8xx_SIMASK_LVM0;
   atexit(Clock_exit);
 }
@@ -134,10 +130,8 @@
 Clock_exit(void)
 {
-  if ( BSP_Configuration.ticks_per_timeslice ) {
-    /* disable PIT and PIT interrupts */
-    m8xx.piscr &= ~(M8xx_PISCR_PTE | M8xx_PISCR_PIE); 
-    
-    (void) set_vector(0, PPC_IRQ_LVL0, 1);
-  }
+  /* disable PIT and PIT interrupts */
+  m8xx.piscr &= ~(M8xx_PISCR_PTE | M8xx_PISCR_PIE); 
+  
+  (void) set_vector(0, PPC_IRQ_LVL0, 1);
 }
 
Index: c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c	(revision e4d7169f1c0d222c9f01e087b4867a846b2e4074)
+++ c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c	(revision 61bd030179f252d14f9639cf4921eb4eee07b5ef)
@@ -47,8 +47,9 @@
  */
 
-#include <bsp.h>
+#include <rtems.h>
 #include <rtems/libio.h>
 #include <mpc8xx.h>
 #include <mpc8xx/console.h>
+#include <mpc8xx/cpm.h>
 #include <stdlib.h>
 #include <unistd.h>
@@ -400,5 +401,5 @@
     if ((RxBd[SCC2_MINOR]->status & M8xx_BD_EMPTY) == 0) {
       rtems_invalidate_multiple_data_cache_lines( 
-        RxBd[SCC2_MINOR]->buffer, 
+        (const void *) RxBd[SCC2_MINOR]->buffer, 
         RxBd[SCC2_MINOR]->length );
       nb_overflow = rtems_termios_enqueue_raw_characters(
@@ -443,5 +444,5 @@
     if ((RxBd[SCC3_MINOR]->status & M8xx_BD_EMPTY) == 0) {
       rtems_invalidate_multiple_data_cache_lines( 
-        RxBd[SCC3_MINOR]->buffer, 
+        (const void *) RxBd[SCC3_MINOR]->buffer, 
         RxBd[SCC3_MINOR]->length );
       nb_overflow = rtems_termios_enqueue_raw_characters(
@@ -485,5 +486,5 @@
     if ((RxBd[SCC4_MINOR]->status & M8xx_BD_EMPTY) == 0) {
       rtems_invalidate_multiple_data_cache_lines( 
-        RxBd[SCC4_MINOR]->buffer, 
+        (const void *) RxBd[SCC4_MINOR]->buffer, 
         RxBd[SCC4_MINOR]->length );
       nb_overflow = rtems_termios_enqueue_raw_characters(
@@ -527,5 +528,5 @@
     if ((RxBd[SMC1_MINOR]->status & M8xx_BD_EMPTY) == 0) {
       rtems_invalidate_multiple_data_cache_lines( 
-        RxBd[SMC1_MINOR]->buffer, 
+        (const void *) RxBd[SMC1_MINOR]->buffer, 
         RxBd[SMC1_MINOR]->length );
       nb_overflow = rtems_termios_enqueue_raw_characters(
@@ -569,5 +570,5 @@
     if ((RxBd[SMC2_MINOR]->status & M8xx_BD_EMPTY) == 0) {
       rtems_invalidate_multiple_data_cache_lines( 
-        RxBd[SMC2_MINOR]->buffer, 
+        (const void *) RxBd[SMC2_MINOR]->buffer, 
         RxBd[SMC2_MINOR]->length );
       nb_overflow = rtems_termios_enqueue_raw_characters(
@@ -984,5 +985,8 @@
     return -1;
   }
-  _CPU_Data_Cache_Block_Invalidate( RxBd[minor]->buffer );
+  rtems_invalidate_multiple_data_cache_lines( 
+    (const void *) RxBd[minor]->buffer,
+    RxBd[minor]->length
+  );
   c = ((char *)RxBd[minor]->buffer)[0];
   RxBd[minor]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP;
@@ -1020,5 +1024,8 @@
       continue;
     txBuf[minor] = *buf++;
-    _CPU_Data_Cache_Block_Flush( &txBuf[minor] );
+    rtems_flush_multiple_data_cache_lines(
+       (const void *) TxBd[minor]->buffer,
+       TxBd[minor]->length
+    );
     TxBd[minor]->buffer = &txBuf[minor];
     TxBd[minor]->length = 1;
Index: c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c	(revision e4d7169f1c0d222c9f01e087b4867a846b2e4074)
+++ c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c	(revision 61bd030179f252d14f9639cf4921eb4eee07b5ef)
@@ -13,11 +13,12 @@
  */
 
-#include <bsp.h>
-#include <rtems/rtems/intr.h>
-#include <rtems/error.h>
+#include <rtems.h>
+#include <mpc8xx.h>
+#include <mpc8xx/cpm.h>
 
 /*
  * Send a command to the CPM RISC processer
  */
+
 void m8xx_cp_execute_cmd( unsigned16 command )
 {
Index: c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c	(revision e4d7169f1c0d222c9f01e087b4867a846b2e4074)
+++ c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c	(revision 61bd030179f252d14f9639cf4921eb4eee07b5ef)
@@ -14,7 +14,7 @@
  */
 
-#include <bsp.h>
-#include <rtems/rtems/intr.h>
-#include <rtems/error.h>
+#include <rtems.h>
+#include <mpc8xx.h>
+#include <mpc8xx/cpm.h>
 
 /*
Index: c/src/lib/libcpu/powerpc/mpc8xx/include/cpm.h
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/include/cpm.h	(revision e4d7169f1c0d222c9f01e087b4867a846b2e4074)
+++ c/src/lib/libcpu/powerpc/mpc8xx/include/cpm.h	(revision 61bd030179f252d14f9639cf4921eb4eee07b5ef)
@@ -19,6 +19,4 @@
 #endif
 
-#include <bsp.h>
-
 /* Functions */
 
Index: c/src/lib/libcpu/powerpc/mpc8xx/include/mmu.h
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/include/mmu.h	(revision e4d7169f1c0d222c9f01e087b4867a846b2e4074)
+++ c/src/lib/libcpu/powerpc/mpc8xx/include/mmu.h	(revision 61bd030179f252d14f9639cf4921eb4eee07b5ef)
@@ -18,6 +18,4 @@
 extern "C" {
 #endif
-
-#include <bsp.h>
 
 /*
Index: c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c	(revision e4d7169f1c0d222c9f01e087b4867a846b2e4074)
+++ c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c	(revision 61bd030179f252d14f9639cf4921eb4eee07b5ef)
@@ -12,5 +12,6 @@
  */
 
-#include <bsp.h>
+#include <rtems.h>
+#include <mpc8xx.h>
 #include <mpc8xx/mmu.h>
 
Index: c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c	(revision e4d7169f1c0d222c9f01e087b4867a846b2e4074)
+++ c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c	(revision 61bd030179f252d14f9639cf4921eb4eee07b5ef)
@@ -44,9 +44,6 @@
  */
 
-#include <bsp.h>
 #include <rtems.h>
 #include <mpc8xx.h>
-
-extern rtems_cpu_table           Cpu_table;             /* owned by BSP */
 
 static volatile rtems_unsigned32 Timer_starting;
@@ -87,8 +84,8 @@
 
   else {
-    if ( total < Cpu_table.timer_least_valid ) {
+    if ( total < rtems_cpu_configuration_get_timer_least_valid() ) {
       return 0;            /* below timer resolution */
     }
-    return (total - Cpu_table.timer_average_overhead);
+    return (total - rtems_cpu_configuration_get_timer_average_overhead());
   }
 }
Index: cpukit/score/cpu/powerpc/rtems/score/ppc.h
===================================================================
--- cpukit/score/cpu/powerpc/rtems/score/ppc.h	(revision e4d7169f1c0d222c9f01e087b4867a846b2e4074)
+++ cpukit/score/cpu/powerpc/rtems/score/ppc.h	(revision 61bd030179f252d14f9639cf4921eb4eee07b5ef)
@@ -384,155 +384,4 @@
 #error "Undefined power of 2 for PPC_CACHE_ALIGNMENT"
 #endif
-
-#ifndef ASM
-
-/*
- * CACHE MANAGER: The following functions are CPU-specific.
- * They provide the basic implementation for the rtems_* cache
- * management routines. If a given function has no meaning for the CPU,
- * it does nothing by default.
- * 
- * FIXME: Some functions simply have not been implemented.
- */
- 
-#if defined(ppc603)			/* And possibly others */
-#define _CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
-#define _CPU_INST_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
-
-/* Helpful macros */
-#define PPC_Get_HID0( _value ) \
-  do { \
-      _value = 0;        /* to avoid warnings */ \
-      asm volatile( \
-          "mfspr %0, 0x3f0;"     /* get HID0 */ \
-          "isync" \
-          : "=r" (_value) \
-          : "0" (_value) \
-      ); \
-  } while (0)
-
-#define PPC_Set_HID0( _value ) \
-  do { \
-      asm volatile( \
-          "isync;" \
-          "mtspr 0x3f0, %0;"     /* load HID0 */ \
-          "isync" \
-          : "=r" (_value) \
-          : "0" (_value) \
-      ); \
-  } while (0)
-
-static inline void _CPU_enable_data_cache (
-	void )
-{
-  unsigned32 value;
-  PPC_Get_HID0( value );
-  value |= 0x00004000;        /* set DCE bit */
-  PPC_Set_HID0( value );
-}
-
-static inline void _CPU_disable_data_cache (
-	void )
-{
-  unsigned32 value;
-  PPC_Get_HID0( value );
-  value &= 0xFFFFBFFF;        /* clear DCE bit */
-  PPC_Set_HID0( value );
-}
-
-static inline void _CPU_enable_inst_cache (
-	void )
-{
-  unsigned32 value;
-  PPC_Get_HID0( value );
-  value |= 0x00008000;       /* Set ICE bit */
-  PPC_Set_HID0( value );
-}
-
-static inline void _CPU_disable_inst_cache (
-	void )
-{
-  unsigned32 value;
-  PPC_Get_HID0( value );
-  value &= 0xFFFF7FFF;       /* Clear ICE bit */
-  PPC_Set_HID0( value );
-}
-
-#elif ( defined(mpc860) || defined(mpc821) )
-
-#define _CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
-#define _CPU_INST_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
-
-#define mtspr(_spr,_reg)   __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) )
-#define isync   __asm__ volatile ("isync\n"::)
-
-static inline void _CPU_flush_1_data_cache_line(
-	const void * _address )
-{
-  register const void *__address = _address;
-  asm volatile ( "dcbf 0,%0" :: "r" (__address) );
-}
-
-static inline void _CPU_invalidate_1_data_cache_line(
-	const void * _address )
-{
-  register const void *__address = _address;
-  asm volatile ( "dcbi 0,%0" :: "r" (__address) );
-}
-
-static inline void _CPU_flush_entire_data_cache ( void ) {}
-static inline void _CPU_invalidate_entire_data_cache ( void ) {}
-static inline void _CPU_freeze_data_cache ( void ) {}
-static inline void _CPU_unfreeze_data_cache ( void ) {}
-
-static inline void _CPU_enable_data_cache (
-	void )
-{
-  unsigned32 r1;
-  r1 = (0x2<<24);
-  mtspr( 568, r1 );
-  isync;
-}
-
-static inline void _CPU_disable_data_cache (
-	void )
-{
-  unsigned32 r1;
-  r1 = (0x4<<24);
-  mtspr( 568, r1 );
-  isync;
-}
-
-static inline void _CPU_invalidate_1_inst_cache_line(
-	const void * _address )
-{
-  register const void *__address = _address;
-  asm volatile ( "icbi 0,%0" :: "r" (__address) );
-}
-
-static inline void _CPU_invalidate_entire_inst_cache ( void ) {}
-static inline void _CPU_freeze_inst_cache ( void ) {}
-static inline void _CPU_unfreeze_inst_cache ( void ) {}
-
-static inline void _CPU_enable_inst_cache (
-	void )
-{
-  unsigned32 r1;
-  r1 = (0x2<<24);
-  mtspr( 560, r1 );
-  isync;
-}
-
-static inline void _CPU_disable_inst_cache (
-	void )
-{
-  unsigned32 r1;
-  r1 = (0x4<<24);
-  mtspr( 560, r1 );
-  isync;
-}
-#endif
-
-#endif  /* !ASM */
 
 /*
