- Timestamp:
- 06/14/00 15:52:24 (23 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- ac815430
- Parents:
- e4d7169f
- Location:
- c/src/lib/libcpu/powerpc
- Files:
-
- 9 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libcpu/powerpc/configure.in
re4d7169f r61bd0301 71 71 mpc6xx/wrapup/Makefile 72 72 shared/Makefile 73 shared/include/Makefile 74 shared/src/Makefile 73 75 wrapup/Makefile) -
c/src/lib/libcpu/powerpc/mpc8xx/clock/clock.c
re4d7169f r61bd0301 37 37 */ 38 38 39 #include < bsp.h>39 #include <rtems.h> 40 40 #include <clockdrv.h> 41 41 #include <rtems/libio.h> … … 43 43 #include <stdlib.h> /* for atexit() */ 44 44 #include <mpc8xx.h> 45 46 extern rtems_cpu_table Cpu_table; /* owned by BSP */47 45 48 46 volatile rtems_unsigned32 Clock_driver_ticks; … … 79 77 Clock_driver_ticks = 0; 80 78 81 pit_value = ( BSP_Configuration.microseconds_per_tick*82 Cpu_table.clicks_per_usec) - 1 ;79 pit_value = (rtems_configuration_get_microseconds_per_tick() * 80 rtems_cpu_configuration_get_clicks_per_usec()) - 1 ; 83 81 84 82 if (pit_value > 0xffff) { /* pit is only 16 bits long */ 85 83 rtems_fatal_error_occurred(-1); 86 84 } 87 if (BSP_Configuration.ticks_per_timeslice) { 88 89 /* 90 * initialize the interval here 91 * First tick is set to right amount of time in the future 92 * Future ticks will be incremented over last value set 93 * in order to provide consistent clicks in the face of 94 * interrupt overhead 95 */ 96 97 rtems_interrupt_catch(clock_isr, PPC_IRQ_LVL0, &previous_isr); 98 99 m8xx.sccr &= ~(1<<24); 100 m8xx.pitc = pit_value; 101 102 /* set PIT irq level, enable PIT, PIT interrupts */ 103 /* and clear int. status */ 104 m8xx.piscr = M8xx_PISCR_PIRQ(0) | 105 M8xx_PISCR_PTE | M8xx_PISCR_PS | M8xx_PISCR_PIE; 85 86 /* 87 * initialize the interval here 88 * First tick is set to right amount of time in the future 89 * Future ticks will be incremented over last value set 90 * in order to provide consistent clicks in the face of 91 * interrupt overhead 92 */ 93 94 rtems_interrupt_catch(clock_isr, PPC_IRQ_LVL0, &previous_isr); 95 96 m8xx.sccr &= ~(1<<24); 97 m8xx.pitc = pit_value; 98 99 /* set PIT irq level, enable PIT, PIT interrupts */ 100 /* and clear int. status */ 101 m8xx.piscr = M8xx_PISCR_PIRQ(0) | 102 M8xx_PISCR_PTE | M8xx_PISCR_PS | M8xx_PISCR_PIE; 106 103 107 104 #ifdef EPPCBUG_SMC1 108 105 simask_copy = m8xx.simask | M8xx_SIMASK_LVM0; 109 106 #endif /* EPPCBUG_SMC1 */ 110 m8xx.simask |= M8xx_SIMASK_LVM0; 111 } 107 m8xx.simask |= M8xx_SIMASK_LVM0; 112 108 atexit(Clock_exit); 113 109 } … … 134 130 Clock_exit(void) 135 131 { 136 if ( BSP_Configuration.ticks_per_timeslice ) { 137 /* disable PIT and PIT interrupts */ 138 m8xx.piscr &= ~(M8xx_PISCR_PTE | M8xx_PISCR_PIE); 139 140 (void) set_vector(0, PPC_IRQ_LVL0, 1); 141 } 132 /* disable PIT and PIT interrupts */ 133 m8xx.piscr &= ~(M8xx_PISCR_PTE | M8xx_PISCR_PIE); 134 135 (void) set_vector(0, PPC_IRQ_LVL0, 1); 142 136 } 143 137 -
c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c
re4d7169f r61bd0301 47 47 */ 48 48 49 #include < bsp.h>49 #include <rtems.h> 50 50 #include <rtems/libio.h> 51 51 #include <mpc8xx.h> 52 52 #include <mpc8xx/console.h> 53 #include <mpc8xx/cpm.h> 53 54 #include <stdlib.h> 54 55 #include <unistd.h> … … 400 401 if ((RxBd[SCC2_MINOR]->status & M8xx_BD_EMPTY) == 0) { 401 402 rtems_invalidate_multiple_data_cache_lines( 402 RxBd[SCC2_MINOR]->buffer,403 (const void *) RxBd[SCC2_MINOR]->buffer, 403 404 RxBd[SCC2_MINOR]->length ); 404 405 nb_overflow = rtems_termios_enqueue_raw_characters( … … 443 444 if ((RxBd[SCC3_MINOR]->status & M8xx_BD_EMPTY) == 0) { 444 445 rtems_invalidate_multiple_data_cache_lines( 445 RxBd[SCC3_MINOR]->buffer,446 (const void *) RxBd[SCC3_MINOR]->buffer, 446 447 RxBd[SCC3_MINOR]->length ); 447 448 nb_overflow = rtems_termios_enqueue_raw_characters( … … 485 486 if ((RxBd[SCC4_MINOR]->status & M8xx_BD_EMPTY) == 0) { 486 487 rtems_invalidate_multiple_data_cache_lines( 487 RxBd[SCC4_MINOR]->buffer,488 (const void *) RxBd[SCC4_MINOR]->buffer, 488 489 RxBd[SCC4_MINOR]->length ); 489 490 nb_overflow = rtems_termios_enqueue_raw_characters( … … 527 528 if ((RxBd[SMC1_MINOR]->status & M8xx_BD_EMPTY) == 0) { 528 529 rtems_invalidate_multiple_data_cache_lines( 529 RxBd[SMC1_MINOR]->buffer,530 (const void *) RxBd[SMC1_MINOR]->buffer, 530 531 RxBd[SMC1_MINOR]->length ); 531 532 nb_overflow = rtems_termios_enqueue_raw_characters( … … 569 570 if ((RxBd[SMC2_MINOR]->status & M8xx_BD_EMPTY) == 0) { 570 571 rtems_invalidate_multiple_data_cache_lines( 571 RxBd[SMC2_MINOR]->buffer,572 (const void *) RxBd[SMC2_MINOR]->buffer, 572 573 RxBd[SMC2_MINOR]->length ); 573 574 nb_overflow = rtems_termios_enqueue_raw_characters( … … 984 985 return -1; 985 986 } 986 _CPU_Data_Cache_Block_Invalidate( RxBd[minor]->buffer ); 987 rtems_invalidate_multiple_data_cache_lines( 988 (const void *) RxBd[minor]->buffer, 989 RxBd[minor]->length 990 ); 987 991 c = ((char *)RxBd[minor]->buffer)[0]; 988 992 RxBd[minor]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP; … … 1020 1024 continue; 1021 1025 txBuf[minor] = *buf++; 1022 _CPU_Data_Cache_Block_Flush( &txBuf[minor] ); 1026 rtems_flush_multiple_data_cache_lines( 1027 (const void *) TxBd[minor]->buffer, 1028 TxBd[minor]->length 1029 ); 1023 1030 TxBd[minor]->buffer = &txBuf[minor]; 1024 1031 TxBd[minor]->length = 1; -
c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c
re4d7169f r61bd0301 13 13 */ 14 14 15 #include < bsp.h>16 #include < rtems/rtems/intr.h>17 #include < rtems/error.h>15 #include <rtems.h> 16 #include <mpc8xx.h> 17 #include <mpc8xx/cpm.h> 18 18 19 19 /* 20 20 * Send a command to the CPM RISC processer 21 21 */ 22 22 23 void m8xx_cp_execute_cmd( unsigned16 command ) 23 24 { -
c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c
re4d7169f r61bd0301 14 14 */ 15 15 16 #include < bsp.h>17 #include < rtems/rtems/intr.h>18 #include < rtems/error.h>16 #include <rtems.h> 17 #include <mpc8xx.h> 18 #include <mpc8xx/cpm.h> 19 19 20 20 /* -
c/src/lib/libcpu/powerpc/mpc8xx/include/cpm.h
re4d7169f r61bd0301 19 19 #endif 20 20 21 #include <bsp.h>22 23 21 /* Functions */ 24 22 -
c/src/lib/libcpu/powerpc/mpc8xx/include/mmu.h
re4d7169f r61bd0301 18 18 extern "C" { 19 19 #endif 20 21 #include <bsp.h>22 20 23 21 /* -
c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c
re4d7169f r61bd0301 12 12 */ 13 13 14 #include <bsp.h> 14 #include <rtems.h> 15 #include <mpc8xx.h> 15 16 #include <mpc8xx/mmu.h> 16 17 -
c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c
re4d7169f r61bd0301 44 44 */ 45 45 46 #include <bsp.h>47 46 #include <rtems.h> 48 47 #include <mpc8xx.h> 49 50 extern rtems_cpu_table Cpu_table; /* owned by BSP */51 48 52 49 static volatile rtems_unsigned32 Timer_starting; … … 87 84 88 85 else { 89 if ( total < Cpu_table.timer_least_valid) {86 if ( total < rtems_cpu_configuration_get_timer_least_valid() ) { 90 87 return 0; /* below timer resolution */ 91 88 } 92 return (total - Cpu_table.timer_average_overhead);89 return (total - rtems_cpu_configuration_get_timer_average_overhead()); 93 90 } 94 91 }
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