Ignore:
Timestamp:
Jul 12, 2016, 10:44:17 AM (4 years ago)
Author:
Joel Sherrill <joel@…>
Branches:
master
Children:
55bde66
Parents:
665f03a
Message:

Misc: Spell length correctly

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h

    r665f03a r612297e8  
    7474#define CPU_INSTRUCTION_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT
    7575#if defined(__ARM_ARCH_7A__)
    76 /* Some/many ARM Cortex-A cores have L1 data line lenght 64 bytes */
     76/* Some/many ARM Cortex-A cores have L1 data line length 64 bytes */
    7777#define CPU_MAXIMAL_CACHE_ALIGNMENT 64
    7878#endif
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