Changeset 6094c1a in rtems


Ignore:
Timestamp:
Sep 11, 2006, 9:46:47 PM (14 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
21d30494
Parents:
158f87b0
Message:

* empty log message *

Location:
c/src
Files:
6 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/i386/shared/comm/i386_io.h

    r158f87b0 r6094c1a  
    11/*
    2 /////////////////////////////////////////////////////////////////////////////
    3 // $Header$
    4 //
    5 // Copyright (c) 2000 - Rosimildo da Silva.  All Rights Reserved.
    6 //
    7 // MODULE DESCRIPTION:
    8 //
    9 // IO Functions for the PC platform equivalent to DOS/Linux. They make
    10 // eaiser the porting of code from these platforms.
    11 //
    12 //  by: Rosimildo da Silva:  rdasilva@connecttel.com
    13 //
    14 /////////////////////////////////////////////////////////////////////////////
    15 */
     2 * $Id$
     3 *
     4 * Copyright (c) 2000 - Rosimildo da Silva.  All Rights Reserved.
     5 *
     6 * MODULE DESCRIPTION:
     7 *
     8 * IO Functions for the PC platform equivalent to DOS/Linux. They make
     9 * eaiser the porting of code from these platforms.
     10 *
     11 *  by: Rosimildo da Silva:  rdasilva@connecttel.com
     12 *
     13 */
    1614
    1715#ifndef i386_io_h__
  • c/src/libchip/network/i82586.c

    r158f87b0 r6094c1a  
    306306
    307307#if I82586_DEBUG
    308   sc->sc_debug = 0; //IED_TINT | IED_XMIT;
     308  sc->sc_debug = 0; /*IED_TINT | IED_XMIT; */
    309309#endif
    310310
  • c/src/libchip/network/i82586reg.h

    r158f87b0 r6094c1a  
    8585
    8686
     87#if 0
    8788/*
    8889 * This is the master configuration block.
    8990 * It tells the hardware where all the rest of the stuff is.
    90  *-
     91 */
    9192struct __ie_sys_conf_ptr {
    92         u_int16_t       mbz;                    // must be zero
    93         u_int8_t        ie_bus_use;             // true if 8-bit only
    94         u_int8_t        mbz2[5];                // must be zero
    95         u_int32_t       ie_iscp_ptr;            // 24-bit physaddr of ISCP
    96 };
    97  */
     93        u_int16_t       mbz;                    /* must be zero */
     94        u_int8_t        ie_bus_use;             /* true if 8-bit only */
     95        u_int8_t        mbz2[5];                /* must be zero */
     96        u_int32_t       ie_iscp_ptr;            /* 24-bit physaddr of ISCP */
     97};
     98#endif
    9899#define IE_SCP_SZ               12
    99100#define IE_SCP_BUS_USE(base)    ((base) + 2)
     
    106107#define IE_SCP_ADDR 0xfffff4
    107108
     109#if 0
    108110/*
    109111 * The tells the hardware where all the rest of the stuff is, too.
    110112 * FIXME: some of these should be re-commented after we figure out their
    111113 * REAL function.
    112  *-
     114 */
    113115struct __ie_int_sys_conf_ptr {
    114116        u_int8_t        ie_busy;        // zeroed after init
     
    117119        caddr_t         ie_base;        // 24-bit physaddr for all 16-bit vars
    118120};
    119  */
     121#endif
    120122#define IE_ISCP_SZ              8
    121123#define IE_ISCP_BUSY(base)      ((base) + 0)
     
    123125#define IE_ISCP_BASE(base)      ((base) + 4)
    124126
     127#if 0
    125128/*
    126129 * This FINALLY tells the hardware what to do and where to put it.
    127  *-
     130 */
    128131struct __ie_sys_ctl_block {
    129132        u_int16_t ie_status;            // status word
     
    136139        u_int16_t ie_err_overrun;       // Overrun errors
    137140};
    138  */
     141#endif
    139142#define IE_SCB_SZ               16
    140143#define IE_SCB_STATUS(base)     ((base) + 0)
     
    187190#define IE_RUS_READY    0x0040  /* receiver is ready */
    188191
     192#if 0
    189193/*
    190194 * This is filled in partially by the chip, partially by us.
    191  *-
     195 */
    192196struct __ie_recv_frame_desc {
    193197        u_int16_t       ie_fd_status;   // status for this frame
     
    200204        u_short         mbz;            // must be zero
    201205};
    202  */
     206#endif
    203207#define IE_RFRAME_SZ                    24
    204208#define IE_RFRAME_ADDR(base,i)          ((base) + (i) * IE_RFRAME_SZ)
     
    230234        "\20\20COMPLT\17BUSY\16OK\14CRC\13ALGN\12RNR\11OVR\10SHORT\7NOEOF"
    231235
     236#if 0
    232237/*
    233238 * linked list of buffers...
    234  *-
     239 */
    235240struct __ie_recv_buf_desc {
    236241        u_int16_t       ie_rbd_status;  // status for this buffer
     
    240245        u_int16_t       mbz;            // must be zero
    241246};
    242  */
     247#endif
    243248#define IE_RBD_SZ                       12
    244249#define IE_RBD_ADDR(base,i)             ((base) + (i) * IE_RBD_SZ)
     
    257262
    258263
     264#if 0
    259265/*
    260266 * All commands share this in common.
    261  *-
     267 */
    262268struct __ie_cmd_common {
    263269        u_int16_t ie_cmd_status;        // status of this command
     
    265271        u_int16_t ie_cmd_link;          // link to next command
    266272};
    267  */
     273#endif
    268274#define IE_CMD_COMMON_SZ                6
    269275#define IE_CMD_COMMON_STATUS(base)      ((base) + 0)
     
    299305
    300306
     307#if 0
    301308/*
    302309 * This is the command to transmit a frame.
    303  *-
     310 */
    304311struct __ie_xmit_cmd {
    305312        struct __ie_cmd_common  com;            // common part
     
    310317        u_int16_t       ie_xmit_length;         // 802.3 length/Ether type field
    311318};
    312  */
     319#endif
    313320#define IE_CMD_XMIT_SZ                  (IE_CMD_COMMON_SZ + 10)
    314321#define IE_CMD_XMIT_ADDR(base,i)        ((base) + (i) * IE_CMD_XMIT_SZ)
     
    335342#define IE_XS_LATECOLL  0x0800  /* Late collision */
    336343
     344#if 0
    337345/*
    338346 * This is a buffer descriptor for a frame to be transmitted.
    339  *-
     347 */
    340348struct __ie_xmit_buf {
    341349        u_int16_t ie_xmit_flags;        // see below
     
    343351        caddr_t ie_xmit_buf;            // 24-pointer to the actual buffer
    344352};
    345  */
     353#endif
    346354#define IE_XBD_SZ                       8
    347355#define IE_XBD_ADDR(base,i)             ((base) + (i) * IE_XBD_SZ)
     
    355363
    356364
     365#if 0
    357366/*
    358367 * Multicast setup command.
    359  *-
     368 */
    360369struct __ie_mcast_cmd {
    361370        struct __ie_cmd_common  com;    // common part
     
    366375        struct __ie_en_addr ie_mcast_addrs[IE_MAXMCAST + 1];// space for them
    367376};
    368  */
     377#endif
    369378#define IE_CMD_MCAST_SZ                 (IE_CMD_COMMON_SZ + 2 /* + XXX */)
    370379#define IE_CMD_MCAST_BYTES(base)        ((base) + IE_CMD_COMMON_SZ + 0)
    371380#define IE_CMD_MCAST_MADDR(base)        ((base) + IE_CMD_COMMON_SZ + 2)
    372381
     382#if 0
    373383/*
    374384 * Time Domain Reflectometer command.
    375  *-
     385 */
    376386struct __ie_tdr_cmd {
    377387        struct __ie_cmd_common com;     // common part
     
    379389        u_short ie_tdr_time;            // error bits and time
    380390};
    381  */
     391#endif
    382392#define IE_CMD_TDR_SZ           (IE_CMD_COMMON_SZ + 2)
    383393#define IE_CMD_TDR_TIME(base)   ((base) + IE_CMD_COMMON_SZ + 0)
     
    389399#define IE_TDR_TIME     0x07ff  /* mask for reflection time */
    390400
     401#if 0
    391402/*
    392403 * Initial Address Setup command
    393  *-
     404 */
    394405struct __ie_iasetup_cmd {
    395406        struct __ie_cmd_common com;
     
    397408        struct __ie_en_addr ie_address;
    398409};
    399  */
     410#endif
    400411#define IE_CMD_IAS_SZ           (IE_CMD_COMMON_SZ + 6)
    401412#define IE_CMD_IAS_EADDR(base)  ((base) + IE_CMD_COMMON_SZ + 0)
    402413
     414#if 0
    403415/*
    404416 * Configuration command
    405  *-
     417 */
    406418struct __ie_config_cmd {
    407419        struct __ie_cmd_common com;     // common part
     
    421433        u_int8_t ie_junk;               // stuff for 82596 (0xff)
    422434};
    423  */
     435#endif
    424436#define IE_CMD_CFG_SZ                   (IE_CMD_COMMON_SZ + 12)
    425437#define IE_CMD_CFG_CNT(base)            ((base) + IE_CMD_COMMON_SZ + 0)
  • c/src/libchip/network/if_dc.c

    r158f87b0 r6094c1a  
    138138 
    139139/* moved to cpukit/include/rtems in CVS current ! */
    140 //#include "if_media.h"
    141 //#include "pci.h"
     140/*#include "if_media.h" */
     141/*#include "pci.h" */
    142142#include <net/if_media.h>
    143143#include <rtems/pci.h>
     
    16161616                if (rc == PCIB_ERR_SUCCESS) {
    16171617                        /* Check the PCI revision */
    1618                         //pcib_conf_read32(t->dc_devsig, DC_PCI_CFRV, &rev);
     1618                        /*pcib_conf_read32(t->dc_devsig, DC_PCI_CFRV, &rev); */
    16191619                        pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
    16201620                                                                        DC_PCI_CFRV, &rev);
     
    19621962         * Map control/status registers.
    19631963         */
    1964         //sig = sc->dc_info->dc_devsig;
     1964        /*sig = sc->dc_info->dc_devsig; */
    19651965        pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
    19661966                                        PCI_COMMAND, &command);
    1967         //pcib_conf_read32(sig, PCI_COMMAND, &command);
     1967        /*pcib_conf_read32(sig, PCI_COMMAND, &command); */
    19681968        command |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
    19691969        pci_write_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
    19701970                                        PCI_COMMAND, command);
    1971         //pcib_conf_write32(sig, PCI_COMMAND, command);
     1971        /*pcib_conf_write32(sig, PCI_COMMAND, command); */
    19721972        pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
    19731973                                        PCI_COMMAND, &command);
    1974         //pcib_conf_read32(sig, PCI_COMMAND, &command);
     1974        /*pcib_conf_read32(sig, PCI_COMMAND, &command); */
    19751975
    19761976#ifdef DC_USEIOSPACE
     
    20032003
    20042004        /* sc->membase is the address of the card's CSRs !!! */
    2005         //pcib_conf_read32(sig, DC_PCI_CFBMA, &value);
     2005        /*pcib_conf_read32(sig, DC_PCI_CFBMA, &value); */
    20062006        pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
    20072007                                        DC_PCI_CFBMA, &value);
     
    20102010        /* Allocate interrupt */
    20112011        memset(&sc->irqInfo, 0, sizeof(rtems_irq_connect_data));
    2012         //pcib_conf_read32(sig, DC_PCI_CFIT, &value);
     2012        /*pcib_conf_read32(sig, DC_PCI_CFIT, &value); */
    20132013        pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
    20142014                                        DC_PCI_CFIT, &value);
     
    20582058        sc->dc_info = dc_devtype(dev);
    20592059        */
    2060         //pcib_conf_read32(sig, DC_PCI_CFRV, &revision);
     2060        /*pcib_conf_read32(sig, DC_PCI_CFRV, &revision); */
    20612061        pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
    20622062                                        DC_PCI_CFRV, &revision);
     
    20832083                sc->dc_pmode = DC_PMODE_MII;
    20842084                /* Increase the latency timer value. */
    2085                 //pcib_conf_read32(sig, DC_PCI_CFLT, &command);
     2085                /*pcib_conf_read32(sig, DC_PCI_CFLT, &command); */
    20862086                pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
    20872087                                                DC_PCI_CFLT, &command);
    20882088                command &= 0xFFFF00FF;
    20892089                command |= 0x00008000;
    2090                 //pcib_conf_write32(sig, DC_PCI_CFLT, command);
     2090                /*pcib_conf_write32(sig, DC_PCI_CFLT, command); */
    20912091                pci_write_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
    20922092                                                DC_PCI_CFLT, command);
     
    21772177        }
    21782178        else {
    2179                 //pcib_conf_read32(sig, DC_PCI_CFLT, &value);
     2179                /*pcib_conf_read32(sig, DC_PCI_CFLT, &value); */
    21802180                pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
    21812181                                                DC_PCI_CFLT, &value);
     
    21882188        /* Take 21143 out of snooze mode */
    21892189        if (DC_IS_INTEL(sc)) {
    2190                 //pcib_conf_read32(sig, DC_PCI_CFDD, &command);
     2190                /*pcib_conf_read32(sig, DC_PCI_CFDD, &command); */
    21912191                pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
    21922192                                                DC_PCI_CFDD, &command);
    21932193                command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE);
    2194                 //pcib_conf_write32(sig, DC_PCI_CFDD, command);
     2194                /*pcib_conf_write32(sig, DC_PCI_CFDD, command); */
    21952195                pci_write_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
    21962196                                                DC_PCI_CFDD, command);
  • c/src/libchip/network/smc91111.c

    r158f87b0 r6094c1a  
    106106                return;
    107107
    108         /*put_reg(cpd, LAN91CXX_INTERRUPT, irq ); *//* ack interrupts */
     108        /*put_reg(cpd, LAN91CXX_INTERRUPT, irq ); */ /* ack interrupts */
    109109
    110110        if (event & LAN91CXX_INTERRUPT_ERCV_INT) {
  • c/src/libchip/network/smc91111.h

    r158f87b0 r6094c1a  
    196196#define LAN91CXX_PHY_CTRL_RST         (1 << 15)
    197197
    198 // PHY Configuration Register 1
    199 #define PHY_CFG1_LNKDIS         0x8000  // 1=Rx Link Detect Function disabled
    200 #define PHY_CFG1_XMTDIS         0x4000  // 1=TP Transmitter Disabled
    201 #define PHY_CFG1_XMTPDN         0x2000  // 1=TP Transmitter Powered Down
    202 #define PHY_CFG1_BYPSCR         0x0400  // 1=Bypass scrambler/descrambler
    203 #define PHY_CFG1_UNSCDS         0x0200  // 1=Unscramble Idle Reception Disable
    204 #define PHY_CFG1_EQLZR          0x0100  // 1=Rx Equalizer Disabled
    205 #define PHY_CFG1_CABLE          0x0080  // 1=STP(150ohm), 0=UTP(100ohm)
    206 #define PHY_CFG1_RLVL0          0x0040  // 1=Rx Squelch level reduced by 4.5db
    207 #define PHY_CFG1_TLVL_SHIFT     2       // Transmit Output Level Adjust
     198/* PHY Configuration Register 1 */
     199#define PHY_CFG1_LNKDIS         0x8000  /* 1=Rx Link Detect Function disabled */
     200#define PHY_CFG1_XMTDIS         0x4000  /* 1=TP Transmitter Disabled */
     201#define PHY_CFG1_XMTPDN         0x2000  /* 1=TP Transmitter Powered Down */
     202#define PHY_CFG1_BYPSCR         0x0400  /* 1=Bypass scrambler/descrambler */
     203#define PHY_CFG1_UNSCDS         0x0200  /* 1=Unscramble Idle Reception Disable */
     204#define PHY_CFG1_EQLZR          0x0100  /* 1=Rx Equalizer Disabled */
     205#define PHY_CFG1_CABLE          0x0080  /* 1=STP(150ohm), 0=UTP(100ohm) */
     206#define PHY_CFG1_RLVL0          0x0040  /* 1=Rx Squelch level reduced by 4.5db */
     207#define PHY_CFG1_TLVL_SHIFT     2       /* Transmit Output Level Adjust */
    208208#define PHY_CFG1_TLVL_MASK      0x003C
    209 #define PHY_CFG1_TRF_MASK       0x0003  // Transmitter Rise/Fall time
    210 
    211 // PHY Configuration Register 2
     209#define PHY_CFG1_TRF_MASK       0x0003  /* Transmitter Rise/Fall time */
     210
     211/* PHY Configuration Register 2 */
    212212#define PHY_CFG2_REG            0x11
    213 #define PHY_CFG2_APOLDIS        0x0020  // 1=Auto Polarity Correction disabled
    214 #define PHY_CFG2_JABDIS         0x0010  // 1=Jabber disabled
    215 #define PHY_CFG2_MREG           0x0008  // 1=Multiple register access (MII mgt)
    216 #define PHY_CFG2_INTMDIO        0x0004  // 1=Interrupt signaled with MDIO pulseo
    217 
    218 // PHY Status Output (and Interrupt status) Register
    219 #define PHY_INT_REG             0x12    // Status Output (Interrupt Status)
    220 #define PHY_INT_INT             0x8000  // 1=bits have changed since last read
    221 #define PHY_INT_LNKFAIL         0x4000  // 1=Link Not detected
    222 #define PHY_INT_LOSSSYNC        0x2000  // 1=Descrambler has lost sync
    223 #define PHY_INT_CWRD            0x1000  // 1=Invalid 4B5B code detected on rx
    224 #define PHY_INT_SSD             0x0800  // 1=No Start Of Stream detected on rx
    225 #define PHY_INT_ESD             0x0400  // 1=No End Of Stream detected on rx
    226 #define PHY_INT_RPOL            0x0200  // 1=Reverse Polarity detected
    227 #define PHY_INT_JAB             0x0100  // 1=Jabber detected
    228 #define PHY_INT_SPDDET          0x0080  // 1=100Base-TX mode, 0=10Base-T mode
    229 #define PHY_INT_DPLXDET         0x0040  // 1=Device in Full Duplex
    230 
    231 // PHY Interrupt/Status Mask Register
    232 #define PHY_MASK_REG            0x13    // Interrupt Mask
     213#define PHY_CFG2_APOLDIS        0x0020  /* 1=Auto Polarity Correction disabled */
     214#define PHY_CFG2_JABDIS         0x0010  /* 1=Jabber disabled */
     215#define PHY_CFG2_MREG           0x0008  /* 1=Multiple register access (MII mgt) */
     216#define PHY_CFG2_INTMDIO        0x0004  /* 1=Interrupt signaled with MDIO pulseo */
     217
     218/* PHY Status Output (and Interrupt status) Register */
     219#define PHY_INT_REG             0x12    /* Status Output (Interrupt Status) */
     220#define PHY_INT_INT             0x8000  /* 1=bits have changed since last read */
     221#define PHY_INT_LNKFAIL         0x4000  /* 1=Link Not detected */
     222#define PHY_INT_LOSSSYNC        0x2000  /* 1=Descrambler has lost sync */
     223#define PHY_INT_CWRD            0x1000  /* 1=Invalid 4B5B code detected on rx */
     224#define PHY_INT_SSD             0x0800  /* 1=No Start Of Stream detected on rx */
     225#define PHY_INT_ESD             0x0400  /* 1=No End Of Stream detected on rx */
     226#define PHY_INT_RPOL            0x0200  /* 1=Reverse Polarity detected */
     227#define PHY_INT_JAB             0x0100  /* 1=Jabber detected */
     228#define PHY_INT_SPDDET          0x0080  /* 1=100Base-TX mode, 0=10Base-T mode */
     229#define PHY_INT_DPLXDET         0x0040  /* 1=Device in Full Duplex */
     230
     231/* PHY Interrupt/Status Mask Register */
     232#define PHY_MASK_REG            0x13    /* Interrupt Mask */
    233233
    234234#define LAN91CXX_RPCR_LEDA_LINK       (0 << 2)
     
    244244#define LAN91CXX_RPCR_SPEED           (1 << 13)
    245245
    246 // PHY Control Register
     246/* PHY Control Register */
    247247#define PHY_CNTL_REG            0x00
    248 #define PHY_CNTL_RST            0x8000  // 1=PHY Reset
    249 #define PHY_CNTL_LPBK           0x4000  // 1=PHY Loopback
    250 #define PHY_CNTL_SPEED          0x2000  // 1=100Mbps, 0=10Mpbs
    251 #define PHY_CNTL_ANEG_EN        0x1000 // 1=Enable Auto negotiation
    252 #define PHY_CNTL_PDN            0x0800  // 1=PHY Power Down mode
    253 #define PHY_CNTL_MII_DIS        0x0400  // 1=MII 4 bit interface disabled
    254 #define PHY_CNTL_ANEG_RST       0x0200 // 1=Reset Auto negotiate
    255 #define PHY_CNTL_DPLX           0x0100  // 1=Full Duplex, 0=Half Duplex
    256 #define PHY_CNTL_COLTST         0x0080  // 1= MII Colision Test
    257 
    258 // PHY Status Register
     248#define PHY_CNTL_RST            0x8000  /* 1=PHY Reset */
     249#define PHY_CNTL_LPBK           0x4000  /* 1=PHY Loopback */
     250#define PHY_CNTL_SPEED          0x2000  /* 1=100Mbps, 0=10Mpbs */
     251#define PHY_CNTL_ANEG_EN        0x1000 /* 1=Enable Auto negotiation */
     252#define PHY_CNTL_PDN            0x0800  /* 1=PHY Power Down mode */
     253#define PHY_CNTL_MII_DIS        0x0400  /* 1=MII 4 bit interface disabled */
     254#define PHY_CNTL_ANEG_RST       0x0200 /* 1=Reset Auto negotiate */
     255#define PHY_CNTL_DPLX           0x0100  /* 1=Full Duplex, 0=Half Duplex */
     256#define PHY_CNTL_COLTST         0x0080  /* 1= MII Colision Test */
     257
     258/* PHY Status Register */
    259259#define PHY_STAT_REG            0x01
    260 #define PHY_STAT_CAP_T4         0x8000  // 1=100Base-T4 capable
    261 #define PHY_STAT_CAP_TXF        0x4000  // 1=100Base-X full duplex capable
    262 #define PHY_STAT_CAP_TXH        0x2000  // 1=100Base-X half duplex capable
    263 #define PHY_STAT_CAP_TF         0x1000  // 1=10Mbps full duplex capable
    264 #define PHY_STAT_CAP_TH         0x0800  // 1=10Mbps half duplex capable
    265 #define PHY_STAT_CAP_SUPR       0x0040  // 1=recv mgmt frames with not preamble
    266 #define PHY_STAT_ANEG_ACK       0x0020  // 1=ANEG has completed
    267 #define PHY_STAT_REM_FLT        0x0010  // 1=Remote Fault detected
    268 #define PHY_STAT_CAP_ANEG       0x0008  // 1=Auto negotiate capable
    269 #define PHY_STAT_LINK           0x0004  // 1=valid link
    270 #define PHY_STAT_JAB            0x0002  // 1=10Mbps jabber condition
    271 #define PHY_STAT_EXREG          0x0001  // 1=extended registers implemented
    272 #define PHY_STAT_RESERVED   0x0780  // Reserved bits mask.
    273 
    274 // PHY Identifier Registers
    275 #define PHY_ID1_REG             0x02    // PHY Identifier 1
    276 #define PHY_ID2_REG             0x03    // PHY Identifier 2
    277 
    278 // PHY Auto-Negotiation Advertisement Register
     260#define PHY_STAT_CAP_T4         0x8000  /* 1=100Base-T4 capable */
     261#define PHY_STAT_CAP_TXF        0x4000  /* 1=100Base-X full duplex capable */
     262#define PHY_STAT_CAP_TXH        0x2000  /* 1=100Base-X half duplex capable */
     263#define PHY_STAT_CAP_TF         0x1000  /* 1=10Mbps full duplex capable */
     264#define PHY_STAT_CAP_TH         0x0800  /* 1=10Mbps half duplex capable */
     265#define PHY_STAT_CAP_SUPR       0x0040  /* 1=recv mgmt frames with not preamble */
     266#define PHY_STAT_ANEG_ACK       0x0020  /* 1=ANEG has completed */
     267#define PHY_STAT_REM_FLT        0x0010  /* 1=Remote Fault detected */
     268#define PHY_STAT_CAP_ANEG       0x0008  /* 1=Auto negotiate capable */
     269#define PHY_STAT_LINK           0x0004  /* 1=valid link */
     270#define PHY_STAT_JAB            0x0002  /* 1=10Mbps jabber condition */
     271#define PHY_STAT_EXREG          0x0001  /* 1=extended registers implemented */
     272#define PHY_STAT_RESERVED   0x0780  /* Reserved bits mask. */
     273
     274/* PHY Identifier Registers */
     275#define PHY_ID1_REG             0x02    /* PHY Identifier 1 */
     276#define PHY_ID2_REG             0x03    /* PHY Identifier 2 */
     277
     278/* PHY Auto-Negotiation Advertisement Register */
    279279#define PHY_AD_REG              0x04
    280 #define PHY_AD_NP               0x8000  // 1=PHY requests exchange of Next Page
    281 #define PHY_AD_ACK              0x4000  // 1=got link code word from remote
    282 #define PHY_AD_RF               0x2000  // 1=advertise remote fault
    283 #define PHY_AD_T4               0x0200  // 1=PHY is capable of 100Base-T4
    284 #define PHY_AD_TX_FDX           0x0100  // 1=PHY is capable of 100Base-TX FDPLX
    285 #define PHY_AD_TX_HDX           0x0080  // 1=PHY is capable of 100Base-TX HDPLX
    286 #define PHY_AD_10_FDX           0x0040  // 1=PHY is capable of 10Base-T FDPLX
    287 #define PHY_AD_10_HDX           0x0020  // 1=PHY is capable of 10Base-T HDPLX
    288 #define PHY_AD_CSMA             0x0001  // 1=PHY is capable of 802.3 CMSA
     280#define PHY_AD_NP               0x8000  /* 1=PHY requests exchange of Next Page */
     281#define PHY_AD_ACK              0x4000  /* 1=got link code word from remote */
     282#define PHY_AD_RF               0x2000  /* 1=advertise remote fault */
     283#define PHY_AD_T4               0x0200  /* 1=PHY is capable of 100Base-T4 */
     284#define PHY_AD_TX_FDX           0x0100  /* 1=PHY is capable of 100Base-TX FDPLX */
     285#define PHY_AD_TX_HDX           0x0080  /* 1=PHY is capable of 100Base-TX HDPLX */
     286#define PHY_AD_10_FDX           0x0040  /* 1=PHY is capable of 10Base-T FDPLX */
     287#define PHY_AD_10_HDX           0x0020  /* 1=PHY is capable of 10Base-T HDPLX */
     288#define PHY_AD_CSMA             0x0001  /* 1=PHY is capable of 802.3 CMSA */
    289289
    290290
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