Changeset 6091f1a6 in rtems


Ignore:
Timestamp:
Feb 7, 2012, 9:11:01 PM (8 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
701f078
Parents:
d6f947e
git-author:
Sebastian Huber <sebastian.huber@…> (02/07/12 21:11:01)
git-committer:
Sebastian Huber <sebastian.huber@…> (02/11/12 20:09:40)
Message:

ARMv7-M NVIC and MPU API changes.

Location:
cpukit/score/cpu/arm
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/arm/armv7m-exception-priority-get.c

    rd6f947e r6091f1a6  
    2525int _ARMV7M_Get_exception_priority( int vector )
    2626{
    27   if (vector >= ARMV7M_VECTOR_IRQ(0)) {
    28     return _ARMV7M_NVIC->ipr [vector - ARMV7M_VECTOR_IRQ(0)];
    29   } else if (vector >= ARMV7M_VECTOR_MEM_MANAGE) {
     27  if ( _ARMV7M_Is_vector_an_irq( vector ) ) {
     28    return _ARMV7M_NVIC_Get_priority( ARMV7M_IRQ_OF_VECTOR( vector ) );
     29  } else if ( vector >= ARMV7M_VECTOR_MEM_MANAGE ) {
    3030    return _ARMV7M_SCB->shpr [vector - 4];
    3131  } else {
  • cpukit/score/cpu/arm/armv7m-exception-priority-set.c

    rd6f947e r6091f1a6  
    2525void _ARMV7M_Set_exception_priority( int vector, int priority )
    2626{
    27   if (vector >= ARMV7M_VECTOR_IRQ(0)) {
    28     _ARMV7M_NVIC->ipr [vector - ARMV7M_VECTOR_IRQ(0)] = (uint8_t) priority;
    29   } else if (vector >= ARMV7M_VECTOR_MEM_MANAGE) {
     27  if ( _ARMV7M_Is_vector_an_irq( vector ) ) {
     28    _ARMV7M_NVIC_Set_priority( ARMV7M_IRQ_OF_VECTOR( vector ), priority );
     29  } else if ( vector >= ARMV7M_VECTOR_MEM_MANAGE ) {
    3030    _ARMV7M_SCB->shpr [vector - 4] = (uint8_t) priority;
    3131  }
  • cpukit/score/cpu/arm/rtems/score/armv7m.h

    rd6f947e r6091f1a6  
    1919
    2020#include <stdint.h>
     21#include <stdbool.h>
    2122
    2223#ifdef __cplusplus
     
    2930  uint32_t actlr;
    3031  uint32_t reserved_1;
    31 } ARMV7M_Interrupt_type;
     32} ARMV7M_ICTAC;
    3233
    3334typedef void (*ARMV7M_Exception_handler)(void);
     
    5455#define ARMV7M_SCB_ICSR_ISRPREEMPT (1U << 23)
    5556#define ARMV7M_SCB_ICSR_ISRPENDING (1U << 22)
    56 #define ARMV7M_SCB_ICSR_VECTPENDING(reg) (((reg) >> 12) & 0x1ffU)
     57#define ARMV7M_SCB_ICSR_VECTPENDING_GET(reg) (((reg) >> 12) & 0x1ffU)
    5758#define ARMV7M_SCB_ICSR_RETTOBASE (1U << 11)
    58 #define ARMV7M_SCB_ICSR_VECTACTIVE(reg) ((reg) & 0x1ffU)
     59#define ARMV7M_SCB_ICSR_VECTACTIVE_GET(reg) ((reg) & 0x1ffU)
    5960  uint32_t icsr;
    6061
     
    105106} ARMV7M_NVIC;
    106107
     108typedef struct {
     109#define ARMV7M_MPU_TYPE_IREGION_GET(reg) (((reg) >> 16) & 0xffU)
     110#define ARMV7M_MPU_TYPE_DREGION_GET(reg) (((reg) >> 8) & 0xffU)
     111#define ARMV7M_MPU_TYPE_SEPARATE (1U << 0)
     112  uint32_t type;
     113
     114#define ARMV7M_MPU_CTRL_PRIVDEFENA (1U << 2)
     115#define ARMV7M_MPU_CTRL_HFNMIENA (1U << 1)
     116#define ARMV7M_MPU_CTRL_ENABLE (1U << 0)
     117  uint32_t ctrl;
     118
     119  uint32_t rnr;
     120
     121#define ARMV7M_MPU_RBAR_ADDR_SHIFT 5
     122#define ARMV7M_MPU_RBAR_ADDR_MASK \
     123  ((0x7ffffffU) << ARMV7M_MPU_RBAR_ADDR_SHIFT)
     124#define ARMV7M_MPU_RBAR_ADDR(val) \
     125  (((val) << ARMV7M_MPU_RBAR_ADDR_SHIFT) & ARMV7M_MPU_RBAR_ADDR_MASK)
     126#define ARMV7M_MPU_RBAR_ADDR_GET(reg) \
     127  (((val) & ARMV7M_MPU_RBAR_ADDR_MASK) >> ARMV7M_MPU_RBAR_ADDR_SHIFT)
     128#define ARMV7M_MPU_RBAR_ADDR_SET(reg, val) \
     129  (((reg) & ~ARMV7M_MPU_RBAR_ADDR_MASK) | ARMV7M_MPU_RBAR_ADDR(val))
     130#define ARMV7M_MPU_RBAR_VALID (1U << 4)
     131#define ARMV7M_MPU_RBAR_REGION_SHIFT 0
     132#define ARMV7M_MPU_RBAR_REGION_MASK \
     133  ((0xfU) << ARMV7M_MPU_RBAR_REGION_SHIFT)
     134#define ARMV7M_MPU_RBAR_REGION(val) \
     135  (((val) << ARMV7M_MPU_RBAR_REGION_SHIFT) & ARMV7M_MPU_RBAR_REGION_MASK)
     136#define ARMV7M_MPU_RBAR_REGION_GET(reg) \
     137  (((val) & ARMV7M_MPU_RBAR_REGION_MASK) >> ARMV7M_MPU_RBAR_REGION_SHIFT)
     138#define ARMV7M_MPU_RBAR_REGION_SET(reg, val) \
     139  (((reg) & ~ARMV7M_MPU_RBAR_REGION_MASK) | ARMV7M_MPU_RBAR_REGION(val))
     140  uint32_t rbar;
     141
     142#define ARMV7M_MPU_RASR_XN (1U << 28)
     143#define ARMV7M_MPU_RASR_AP_SHIFT 24
     144#define ARMV7M_MPU_RASR_AP_MASK \
     145  ((0x7U) << ARMV7M_MPU_RASR_AP_SHIFT)
     146#define ARMV7M_MPU_RASR_AP(val) \
     147  (((val) << ARMV7M_MPU_RASR_AP_SHIFT) & ARMV7M_MPU_RASR_AP_MASK)
     148#define ARMV7M_MPU_RASR_AP_GET(reg) \
     149  (((val) & ARMV7M_MPU_RASR_AP_MASK) >> ARMV7M_MPU_RASR_AP_SHIFT)
     150#define ARMV7M_MPU_RASR_AP_SET(reg, val) \
     151  (((reg) & ~ARMV7M_MPU_RASR_AP_MASK) | ARMV7M_MPU_RASR_AP(val))
     152#define ARMV7M_MPU_RASR_TEX_SHIFT 19
     153#define ARMV7M_MPU_RASR_TEX_MASK \
     154  ((0x7U) << ARMV7M_MPU_RASR_TEX_SHIFT)
     155#define ARMV7M_MPU_RASR_TEX(val) \
     156  (((val) << ARMV7M_MPU_RASR_TEX_SHIFT) & ARMV7M_MPU_RASR_TEX_MASK)
     157#define ARMV7M_MPU_RASR_TEX_GET(reg) \
     158  (((val) & ARMV7M_MPU_RASR_TEX_MASK) >> ARMV7M_MPU_RASR_TEX_SHIFT)
     159#define ARMV7M_MPU_RASR_TEX_SET(reg, val) \
     160  (((reg) & ~ARMV7M_MPU_RASR_TEX_MASK) | ARMV7M_MPU_RASR_TEX(val))
     161#define ARMV7M_MPU_RASR_S (1U << 18)
     162#define ARMV7M_MPU_RASR_C (1U << 17)
     163#define ARMV7M_MPU_RASR_B (1U << 16)
     164#define ARMV7M_MPU_RASR_SRD_SHIFT 8
     165#define ARMV7M_MPU_RASR_SRD_MASK \
     166  ((0xffU) << ARMV7M_MPU_RASR_SRD_SHIFT)
     167#define ARMV7M_MPU_RASR_SRD(val) \
     168  (((val) << ARMV7M_MPU_RASR_SRD_SHIFT) & ARMV7M_MPU_RASR_SRD_MASK)
     169#define ARMV7M_MPU_RASR_SRD_GET(reg) \
     170  (((val) & ARMV7M_MPU_RASR_SRD_MASK) >> ARMV7M_MPU_RASR_SRD_SHIFT)
     171#define ARMV7M_MPU_RASR_SRD_SET(reg, val) \
     172  (((reg) & ~ARMV7M_MPU_RASR_SRD_MASK) | ARMV7M_MPU_RASR_SRD(val))
     173#define ARMV7M_MPU_RASR_SIZE_SHIFT 1
     174#define ARMV7M_MPU_RASR_SIZE_MASK \
     175  ((0x1fU) << ARMV7M_MPU_RASR_SIZE_SHIFT)
     176#define ARMV7M_MPU_RASR_SIZE(val) \
     177  (((val) << ARMV7M_MPU_RASR_SIZE_SHIFT) & ARMV7M_MPU_RASR_SIZE_MASK)
     178#define ARMV7M_MPU_RASR_SIZE_GET(reg) \
     179  (((val) & ARMV7M_MPU_RASR_SIZE_MASK) >> ARMV7M_MPU_RASR_SIZE_SHIFT)
     180#define ARMV7M_MPU_RASR_SIZE_SET(reg, val) \
     181  (((reg) & ~ARMV7M_MPU_RASR_SIZE_MASK) | ARMV7M_MPU_RASR_SIZE(val))
     182#define ARMV7M_MPU_RASR_ENABLE (1U << 0)
     183  uint32_t rasr;
     184
     185  uint32_t rbar_a1;
     186  uint32_t rasr_a1;
     187  uint32_t rbar_a2;
     188  uint32_t rasr_a2;
     189  uint32_t rbar_a3;
     190  uint32_t rasr_a3;
     191} ARMV7M_MPU;
     192
     193typedef enum {
     194  ARMV7M_MPU_AP_PRIV_NO_USER_NO,
     195  ARMV7M_MPU_AP_PRIV_RW_USER_NO,
     196  ARMV7M_MPU_AP_PRIV_RW_USER_RO,
     197  ARMV7M_MPU_AP_PRIV_RW_USER_RW,
     198  ARMV7M_MPU_AP_PRIV_RO_USER_NO = 0x5,
     199  ARMV7M_MPU_AP_PRIV_RO_USER_RO,
     200} ARMV7M_MPU_Access_permissions;
     201
     202typedef enum {
     203  ARMV7M_MPU_ATTR_R = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RO_USER_NO)
     204    | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_XN,
     205  ARMV7M_MPU_ATTR_RW = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RW_USER_NO)
     206    | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_XN | ARMV7M_MPU_RASR_B,
     207  ARMV7M_MPU_ATTR_RWX = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RW_USER_NO)
     208    | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B,
     209  ARMV7M_MPU_ATTR_X = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_NO_USER_NO)
     210    | ARMV7M_MPU_RASR_C,
     211  ARMV7M_MPU_ATTR_RX = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RO_USER_NO)
     212    | ARMV7M_MPU_RASR_C,
     213  ARMV7M_MPU_ATTR_IO = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RW_USER_NO)
     214    | ARMV7M_MPU_RASR_XN,
     215} ARMV7M_MPU_Attributes;
     216
     217typedef enum {
     218  ARMV7M_MPU_SIZE_32_B = 0x4,
     219  ARMV7M_MPU_SIZE_64_B,
     220  ARMV7M_MPU_SIZE_128_B,
     221  ARMV7M_MPU_SIZE_256_B,
     222  ARMV7M_MPU_SIZE_512_B,
     223  ARMV7M_MPU_SIZE_1_KB,
     224  ARMV7M_MPU_SIZE_2_KB,
     225  ARMV7M_MPU_SIZE_4_KB,
     226  ARMV7M_MPU_SIZE_8_KB,
     227  ARMV7M_MPU_SIZE_16_KB,
     228  ARMV7M_MPU_SIZE_32_KB,
     229  ARMV7M_MPU_SIZE_64_KB,
     230  ARMV7M_MPU_SIZE_128_KB,
     231  ARMV7M_MPU_SIZE_256_KB,
     232  ARMV7M_MPU_SIZE_512_KB,
     233  ARMV7M_MPU_SIZE_1_MB,
     234  ARMV7M_MPU_SIZE_2_MB,
     235  ARMV7M_MPU_SIZE_4_MB,
     236  ARMV7M_MPU_SIZE_8_MB,
     237  ARMV7M_MPU_SIZE_16_MB,
     238  ARMV7M_MPU_SIZE_32_MB,
     239  ARMV7M_MPU_SIZE_64_MB,
     240  ARMV7M_MPU_SIZE_128_MB,
     241  ARMV7M_MPU_SIZE_256_MB,
     242  ARMV7M_MPU_SIZE_512_MB,
     243  ARMV7M_MPU_SIZE_1_GB,
     244  ARMV7M_MPU_SIZE_2_GB,
     245  ARMV7M_MPU_SIZE_4_GB
     246} ARMV7M_MPU_Size;
     247
     248typedef struct {
     249  uint32_t rbar;
     250  uint32_t rasr;
     251} ARMV7M_MPU_Region;
     252
     253#define ARMV7M_MPU_REGION_INITIALIZER(idx, addr, size, attr) \
     254  { \
     255    ((addr) & ARMV7M_MPU_RBAR_ADDR_MASK) \
     256      | ARMV7M_MPU_RBAR_VALID \
     257      | ARMV7M_MPU_RBAR_REGION(idx), \
     258    ARMV7M_MPU_RASR_SIZE(size) | (attr) | ARMV7M_MPU_RASR_ENABLE \
     259  }
     260
     261#define ARMV7M_MPU_REGION_DISABLED_INITIALIZER(idx) \
     262  { \
     263    ARMV7M_MPU_RBAR_VALID | ARMV7M_MPU_RBAR_REGION(idx), \
     264    0 \
     265  }
     266
    107267#define ARMV7M_SCS_BASE 0xe000e000
     268#define ARMV7M_ICTAC_BASE (ARMV7M_SCS_BASE + 0x0)
    108269#define ARMV7M_SYSTICK_BASE (ARMV7M_SCS_BASE + 0x10)
    109270#define ARMV7M_NVIC_BASE (ARMV7M_SCS_BASE + 0x100)
    110271#define ARMV7M_SCB_BASE (ARMV7M_SCS_BASE + 0xd00)
    111 
    112 #define _ARMV7M_Interrupt_type \
    113   ((volatile ARMV7M_Interrupt_type *) ARMV7M_SCS_BASE)
     272#define ARMV7M_MPU_BASE (ARMV7M_SCS_BASE + 0xd90)
     273
     274#define _ARMV7M_ICTAC \
     275  ((volatile ARMV7M_ICTAC *) ARMV7M_ICTAC_BASE)
    114276#define _ARMV7M_SCB \
    115277  ((volatile ARMV7M_SCB *) ARMV7M_SCB_BASE)
     
    118280#define _ARMV7M_NVIC \
    119281  ((volatile ARMV7M_NVIC *) ARMV7M_NVIC_BASE)
     282#define _ARMV7M_MPU \
     283  ((volatile ARMV7M_MPU *) ARMV7M_MPU_BASE)
    120284
    121285#define ARMV7M_VECTOR_MSP 0
     
    130294#define ARMV7M_VECTOR_PENDSV 14
    131295#define ARMV7M_VECTOR_SYSTICK 15
    132 #define ARMV7M_VECTOR_IRQ(n) (16 + (n))
     296#define ARMV7M_VECTOR_IRQ(n) ((n) + 16)
     297#define ARMV7M_IRQ_OF_VECTOR(n) ((n) - 16)
     298
     299static inline bool _ARMV7M_Is_vector_an_irq( int vector )
     300{
     301  return vector >= 16;
     302}
    133303
    134304static inline uint32_t _ARMV7M_Get_basepri(void)
     
    209379  __asm__ volatile ("mrs %[val], xpsr\n" : [val] "=&r" (val));
    210380  return val;
     381}
     382
     383static inline bool _ARMV7M_NVIC_Is_enabled( int irq )
     384{
     385  int index = irq >> 5;
     386  uint32_t bit = 1U << (irq & 0x1f);
     387
     388  return (_ARMV7M_NVIC->iser [index] & bit) != 0;
     389}
     390
     391static inline void _ARMV7M_NVIC_Set_enable( int irq )
     392{
     393  int index = irq >> 5;
     394  uint32_t bit = 1U << (irq & 0x1f);
     395
     396  _ARMV7M_NVIC->iser [index] = bit;
     397}
     398
     399static inline void _ARMV7M_NVIC_Clear_enable( int irq )
     400{
     401  int index = irq >> 5;
     402  uint32_t bit = 1U << (irq & 0x1f);
     403
     404  _ARMV7M_NVIC->icer [index] = bit;
     405}
     406
     407static inline bool _ARMV7M_NVIC_Is_pending( int irq )
     408{
     409  int index = irq >> 5;
     410  uint32_t bit = 1U << (irq & 0x1f);
     411
     412  return (_ARMV7M_NVIC->ispr [index] & bit) != 0;
     413}
     414
     415static inline void _ARMV7M_NVIC_Set_pending( int irq )
     416{
     417  int index = irq >> 5;
     418  uint32_t bit = 1U << (irq & 0x1f);
     419
     420  _ARMV7M_NVIC->ispr [index] = bit;
     421}
     422
     423static inline void _ARMV7M_NVIC_Clear_pending( int irq )
     424{
     425  int index = irq >> 5;
     426  uint32_t bit = 1U << (irq & 0x1f);
     427
     428  _ARMV7M_NVIC->icpr [index] = bit;
     429}
     430
     431static inline bool _ARMV7M_NVIC_Is_active( int irq )
     432{
     433  int index = irq >> 5;
     434  uint32_t bit = 1U << (irq & 0x1f);
     435
     436  return (_ARMV7M_NVIC->iabr [index] & bit) != 0;
     437}
     438
     439static inline void _ARMV7M_NVIC_Set_priority( int irq, int priority )
     440{
     441  _ARMV7M_NVIC->ipr [irq] = (uint8_t) priority;
     442}
     443
     444static inline int _ARMV7M_NVIC_Get_priority( int irq )
     445{
     446  return _ARMV7M_NVIC->ipr [irq];
    211447}
    212448
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