Changeset 5f652cb2 in rtems


Ignore:
Timestamp:
Jul 26, 2021, 8:43:00 PM (3 months ago)
Author:
Kinsey Moore <kinsey.moore@…>
Branches:
master
Children:
c2f24048
Parents:
670a508
git-author:
Kinsey Moore <kinsey.moore@…> (07/26/21 20:43:00)
git-committer:
Joel Sherrill <joel@…> (09/21/21 13:58:32)
Message:

cpukit: Add AArch64 SMP Support

This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.

Files:
2 added
15 edited

Legend:

Unmodified
Added
Removed
  • bsps/aarch64/include/bsp/aarch64-mmu.h

    r670a508 r5f652cb2  
    386386
    387387BSP_START_TEXT_SECTION static inline void
    388 aarch64_mmu_setup_translation_table_and_enable(
    389   const aarch64_mmu_config_entry *config_table,
    390   size_t config_count
    391 )
     388aarch64_mmu_enable( void )
    392389{
    393390  uint64_t sctlr;
    394391
    395   aarch64_mmu_setup_translation_table(
    396     config_table,
    397     config_count
    398   );
     392  /* CPUECTLR_EL1.SMPEN is already set on ZynqMP and is not writable */
     393
     394  /* Invalidate cache */
     395  rtems_cache_invalidate_entire_data();
    399396
    400397  /* Enable MMU and cache */
  • bsps/aarch64/shared/start/start.S

    r670a508 r5f652cb2  
    167167  /* Read MPIDR and get current processor index */
    168168  mrs x7, mpidr_el1
    169   and x7, #0xff
     169  and x7, x7, #0xff
    170170#endif
    171171
     
    173173  /*
    174174   * Get current per-CPU control and store it in PL1 only Thread ID
    175    * Register (TPIDRPRW).
     175   * Register (TPIDR_EL1).
    176176   */
    177177#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
     
    180180  ldr x1, =_Per_CPU_Information
    181181#endif
    182   add x1, x1, x7, asl #PER_CPU_CONTROL_SIZE_LOG2
    183   mcr p15, 0, x1, c13, c0, 4
     182  add x1, x1, x7, lsl #PER_CPU_CONTROL_SIZE_LOG2
     183  msr TPIDR_EL1, x1
    184184
    185185#endif
     
    202202  add x3, x1, x2
    203203
    204   /* Save original DAIF value */
    205   mrs  x4, DAIF
     204  /* Disable interrupts */
     205  msr DAIFSet, #0x2
    206206
    207207#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
  • bsps/aarch64/xilinx-versal/start/bspstartmmu.c

    r670a508 r5f652cb2  
    7171  aarch64_mmu_setup();
    7272
    73   aarch64_mmu_setup_translation_table_and_enable(
     73  aarch64_mmu_setup_translation_table(
    7474    &versal_mmu_config_table[ 0 ],
    7575    RTEMS_ARRAY_SIZE( versal_mmu_config_table )
    7676  );
     77
     78  aarch64_mmu_enable();
    7779}
  • bsps/aarch64/xilinx-zynqmp/include/bsp.h

    r670a508 r5f652cb2  
    6161
    6262#define BSP_RESET_SMC
     63#define BSP_CPU_ON_USES_SMC
    6364
    6465/**
     
    6869 */
    6970BSP_START_TEXT_SECTION void zynqmp_setup_mmu_and_cache(void);
     71
     72/**
     73 * @brief Zynq UltraScale+ MPSoC specific set up of the MMU for non-primary
     74 * cores.
     75 *
     76 * Provide in the application to override the defaults in the BSP.
     77 */
     78BSP_START_TEXT_SECTION void zynqmp_setup_secondary_cpu_mmu_and_cache( void );
    7079
    7180void zynqmp_debug_console_flush(void);
  • bsps/aarch64/xilinx-zynqmp/start/bspstarthooks.c

    r670a508 r5f652cb2  
    3939#include <bsp/start.h>
    4040
    41 BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
     41#ifdef RTEMS_SMP
     42#include <rtems/score/aarch64-system-registers.h>
     43#include <rtems/score/smpimpl.h>
     44
     45#include <bsp/irq-generic.h>
     46#endif
     47
     48BSP_START_TEXT_SECTION void bsp_start_hook_0( void )
    4249{
    43   /* Do nothing */
     50#ifdef RTEMS_SMP
     51  uint32_t cpu_index_self;
     52
     53  cpu_index_self = _SMP_Get_current_processor();
     54
     55  if ( cpu_index_self != 0 ) {
     56    if (
     57      cpu_index_self >= rtems_configuration_get_maximum_processors()
     58      || !_SMP_Should_start_processor( cpu_index_self )
     59    ) {
     60      while ( true ) {
     61        _AARCH64_Wait_for_event();
     62      }
     63    }
     64
     65    /* Change the VBAR from the start to the normal vector table */
     66    AArch64_start_set_vector_base();
     67
     68    zynqmp_setup_secondary_cpu_mmu_and_cache();
     69    arm_gic_irq_initialize_secondary_cpu();
     70
     71    bsp_interrupt_vector_enable( ARM_GIC_IRQ_SGI_0 );
     72    _SMP_Start_multitasking_on_secondary_processor(
     73      _Per_CPU_Get_by_index( cpu_index_self )
     74    );
     75  }
     76
     77#endif
    4478}
    4579
    46 BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
     80BSP_START_TEXT_SECTION void bsp_start_hook_1( void )
    4781{
    4882  AArch64_start_set_vector_base();
  • bsps/aarch64/xilinx-zynqmp/start/bspstartmmu.c

    r670a508 r5f652cb2  
    4242zynqmp_mmu_config_table[] = {
    4343  AARCH64_MMU_DEFAULT_SECTIONS,
    44 #if defined( RTEMS_SMP )
    45   {
    46     .begin = 0xffff0000U,
    47     .end = 0xffffffffU,
    48     .flags = AARCH64_MMU_DEVICE
    49   },
    50 #endif
    5144  {
    5245    .begin = 0xf9000000U,
     
    7164  aarch64_mmu_setup();
    7265
    73   aarch64_mmu_setup_translation_table_and_enable(
     66  aarch64_mmu_setup_translation_table(
    7467    &zynqmp_mmu_config_table[ 0 ],
    7568    RTEMS_ARRAY_SIZE( zynqmp_mmu_config_table )
    7669  );
     70
     71  aarch64_mmu_enable();
    7772}
     73
     74/*
     75 * Make weak and let the user override.
     76 */
     77BSP_START_TEXT_SECTION void zynqmp_setup_secondary_cpu_mmu_and_cache( void )
     78__attribute__ ( ( weak ) );
     79
     80BSP_START_TEXT_SECTION void zynqmp_setup_secondary_cpu_mmu_and_cache( void )
     81{
     82  /* Perform basic MMU setup */
     83  aarch64_mmu_setup();
     84
     85  /* Use the existing root page table already configured by CPU0 */
     86  _AArch64_Write_ttbr0_el1( (uintptr_t) bsp_translation_table_base );
     87
     88  aarch64_mmu_enable();
     89}
  • cpukit/score/cpu/aarch64/aarch64-exception-interrupt.S

    r670a508 r5f652cb2  
    4848
    4949#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
    50   #define SELF_CPU_CONTROL_GET_REG w19
     50  #ifdef RTEMS_SMP
     51    #define SELF_CPU_CONTROL_GET_REG x19
     52  #else
     53    #define SELF_CPU_CONTROL_GET_REG w19
     54  #endif
    5155#else
    5256  #define SELF_CPU_CONTROL_GET_REG x19
  • cpukit/score/cpu/aarch64/cpu_asm.S

    r670a508 r5f652cb2  
    5656 */
    5757
    58 #ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
    59 #define reg_2 w2
     58DEFINE_FUNCTION_AARCH64(_CPU_Context_switch)
     59        .globl  _CPU_Context_switch_no_return
     60        .set    _CPU_Context_switch_no_return, _CPU_Context_switch
     61#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
     62/* Sanitize inputs for ILP32 ABI */
     63        mov w0, w0
     64        mov w1, w1
     65  #ifdef RTEMS_SMP
     66    #define reg_2 x2
     67  #else
     68    #define reg_2 w2
     69  #endif
    6070#else
    6171#define reg_2 x2
    6272#endif
    6373
    64 DEFINE_FUNCTION_AARCH64(_CPU_Context_switch)
    6574/* Start saving context */
    6675        GET_SELF_CPU_CONTROL    reg_2
     
    8796
    8897#ifdef RTEMS_SMP
    89 #error SMP not yet supported
     98        /*
     99         * The executing thread no longer executes on this processor.  Switch
     100         * the stack to the temporary interrupt stack of this processor.  Mark
     101         * the context of the executing thread as not executing.
     102         */
     103        dmb     SY
     104        add     sp, x2, #(PER_CPU_INTERRUPT_FRAME_AREA + CPU_INTERRUPT_FRAME_SIZE)
     105        mov     x3, #0
     106        strb    w3, [x0, #AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET]
     107
     108.L_check_is_executing:
     109
     110        /* Check the is executing indicator of the heir context */
     111        add     x3, x1, #AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET
     112        ldaxrb  w4, [x3]
     113        cmp     x4, #0
     114        bne     .L_get_potential_new_heir
     115
     116        /* Try to update the is executing indicator of the heir context */
     117        mov     x4, #1
     118        stlxrb  w5, w4, [x3]
     119        cmp     x5, #0
     120        bne     .L_get_potential_new_heir
     121        dmb     SY
    90122#endif
    91123
     
    130162 */
    131163DEFINE_FUNCTION_AARCH64(_CPU_Context_restore)
     164#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
     165/* Sanitize input for ILP32 ABI */
     166        mov w0, w0
     167#endif
     168
    132169        mov     x1, x0
    133170        GET_SELF_CPU_CONTROL    reg_2
    134171        b       .L_restore
     172
     173#ifdef RTEMS_SMP
     174.L_get_potential_new_heir:
     175
     176        /* We may have a new heir */
     177
     178        /* Read the executing and heir */
     179#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
     180        ldr     w4, [x2, #PER_CPU_OFFSET_EXECUTING]
     181        ldr     w5, [x2, #PER_CPU_OFFSET_HEIR]
     182#else
     183        ldr     x4, [x2, #PER_CPU_OFFSET_EXECUTING]
     184        ldr     x5, [x2, #PER_CPU_OFFSET_HEIR]
     185#endif
     186
     187        /*
     188         * Update the executing only if necessary to avoid cache line
     189         * monopolization.
     190         */
     191        cmp     x4, x5
     192        beq     .L_check_is_executing
     193
     194        /* Calculate the heir context pointer */
     195        sub     x4, x1, x4
     196        add     x1, x5, x4
     197
     198        /* Update the executing */
     199#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
     200        str     w5, [x2, #PER_CPU_OFFSET_EXECUTING]
     201#else
     202        str     x5, [x2, #PER_CPU_OFFSET_EXECUTING]
     203#endif
     204
     205        b       .L_check_is_executing
     206#endif
  • cpukit/score/cpu/aarch64/include/rtems/asm.h

    r670a508 r5f652cb2  
    8282
    8383.macro GET_SELF_CPU_CONTROL REG
     84#ifdef RTEMS_SMP
     85        /* Use Thread ID Register (TPIDR_EL1) */
     86        mrs     \REG, TPIDR_EL1
     87#else
    8488        ldr     \REG, =_Per_CPU_Information
     89#endif
    8590.endm
    8691
  • cpukit/score/cpu/aarch64/include/rtems/score/cpu.h

    r670a508 r5f652cb2  
    135135#ifdef RTEMS_SMP
    136136  #if defined(AARCH64_MULTILIB_VFP)
    137     #define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x70
     137    #define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0xb8
    138138  #else
    139     #define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x30
     139    #define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x78
    140140  #endif
    141141#endif
     
    192192static inline void _AARCH64_Data_memory_barrier( void )
    193193{
    194   __asm__ volatile ( "dmb LD" : : : "memory" );
     194  __asm__ volatile ( "dmb SY" : : : "memory" );
    195195}
    196196
    197197static inline void _AARCH64_Data_synchronization_barrier( void )
    198198{
    199   __asm__ volatile ( "dsb LD" : : : "memory" );
     199  __asm__ volatile ( "dsb SY" : : : "memory" );
    200200}
    201201
     
    313313 */
    314314void _CPU_Context_switch( Context_Control *run, Context_Control *heir );
     315
     316RTEMS_NO_RETURN void _CPU_Context_switch_no_return(
     317  Context_Control *executing,
     318  Context_Control *heir
     319);
    315320
    316321RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context );
  • cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h

    r670a508 r5f652cb2  
    5151
    5252#define CPU_PER_CPU_CONTROL_SIZE 0
    53 #define CPU_INTERRUPT_FRAME_SIZE 240
     53#define CPU_INTERRUPT_FRAME_SIZE 0x2E0
    5454
    5555#ifndef ASM
     
    6060
    6161RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
     62
     63typedef struct {
     64  uint64_t x0;
     65  uint64_t register_lr_original;
     66  uint64_t register_lr;
     67  uint64_t x1;
     68  uint64_t x2;
     69  uint64_t x3;
     70  uint64_t x4;
     71  uint64_t x5;
     72  uint64_t x6;
     73  uint64_t x7;
     74  uint64_t x8;
     75  uint64_t x9;
     76  uint64_t x10;
     77  uint64_t x11;
     78  uint64_t x12;
     79  uint64_t x13;
     80  uint64_t x14;
     81  uint64_t x15;
     82  uint64_t x16;
     83  uint64_t x17;
     84  uint64_t x18;
     85  uint64_t x19;
     86  uint64_t x20;
     87  uint64_t x21;
     88#ifdef AARCH64_MULTILIB_VFP
     89  uint128_t q0;
     90  uint128_t q1;
     91  uint128_t q2;
     92  uint128_t q3;
     93  uint128_t q4;
     94  uint128_t q5;
     95  uint128_t q6;
     96  uint128_t q7;
     97  uint128_t q8;
     98  uint128_t q9;
     99  uint128_t q10;
     100  uint128_t q11;
     101  uint128_t q12;
     102  uint128_t q13;
     103  uint128_t q14;
     104  uint128_t q15;
     105  uint128_t q16;
     106  uint128_t q17;
     107  uint128_t q18;
     108  uint128_t q19;
     109  uint128_t q20;
     110  uint128_t q21;
     111  uint128_t q22;
     112  uint128_t q23;
     113  uint128_t q24;
     114  uint128_t q25;
     115  uint128_t q26;
     116  uint128_t q27;
     117  uint128_t q28;
     118  uint128_t q29;
     119  uint128_t q30;
     120  uint128_t q31;
     121#endif /* AARCH64_MULTILIB_VFP */
     122  uint64_t register_elr;
     123  uint64_t register_spsr;
     124  uint64_t register_fpsr;
     125  uint64_t register_fpcr;
     126} CPU_Interrupt_frame;
    62127
    63128void _CPU_Context_volatile_clobber( uintptr_t pattern );
  • spec/build/bsps/aarch64/xilinx-zynqmp/abi.yml

    r670a508 r5f652cb2  
    99default:
    1010- -mcpu=cortex-a53
     11- -mno-outline-atomics
    1112default-by-variant:
    1213- value:
    1314  - -mcpu=cortex-a53
     15  - -mno-outline-atomics
    1416  - -mabi=ilp32
    1517  variants:
  • spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml

    r670a508 r5f652cb2  
    2020- role: build-dependency
    2121  uid: obj
     22- role: build-dependency
     23  uid: objsmp
    2224- role: build-dependency
    2325  uid: optloadoff
  • spec/build/cpukit/optsmp.yml

    r670a508 r5f652cb2  
    1212  Enable the Symmetric Multiprocessing (SMP) support
    1313enabled-by:
     14- aarch64/xilinx_zynqmp_ilp32_qemu
     15- aarch64/xilinx_zynqmp_ilp32_zu3eg
     16- aarch64/xilinx_zynqmp_lp64_qemu
     17- aarch64/xilinx_zynqmp_lp64_zu3eg
    1418- arm/altcycv_devkit
    1519- arm/fvp_cortex_r52
  • testsuites/smptests/smpfatal08/init.c

    r670a508 r5f652cb2  
    7777#if defined(RTEMS_PARAVIRT) \
    7878  || (!defined(__leon__) && !defined(__PPC__) \
    79     && !defined(__arm__) && !defined(__riscv))
     79    && !defined(__arm__) && !defined(__riscv) && !defined(__aarch64__))
    8080uint32_t _CPU_SMP_Get_current_processor(void)
    8181{
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