Changeset 5f4f828 in rtems


Ignore:
Timestamp:
Nov 19, 2014, 1:55:53 PM (5 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
d1eb7b1
Parents:
e492e7f8
git-author:
Sebastian Huber <sebastian.huber@…> (11/19/14 13:55:53)
git-committer:
Sebastian Huber <sebastian.huber@…> (11/20/14 09:30:28)
Message:

bsps/arm: L1 cache support changes

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h

    re492e7f8 r5f4f828  
    2626#define LIBBSP_ARM_SHARED_CACHE_L1_H
    2727
    28 #include <assert.h>
    2928#include <bsp.h>
    3029#include <libcpu/arm-cp15.h>
     
    4746
    4847/* Errata Handlers */
    49 #define ARM_CACHE_L1_ERRATA_764369_HANDLER()                 \
    50   if( arm_errata_is_applicable_processor_errata_764369() ) { \
    51     _ARM_Data_synchronization_barrier();                     \
    52   }
    53 
    54    
     48static void arm_cache_l1_errata_764369_handler( void )
     49{
     50#ifdef RTEMS_SMP
     51  _ARM_Data_synchronization_barrier();
     52#endif
     53}
     54
    5555static void arm_cache_l1_select( const uint32_t selection )
    5656{
     
    224224      (uint32_t)( (size_t) d_addr + n_bytes - 1 );
    225225
    226     ARM_CACHE_L1_ERRATA_764369_HANDLER();
     226    arm_cache_l1_errata_764369_handler();
    227227
    228228    for (; adx <= ADDR_LAST; adx += ARM_CACHE_L1_CPU_DATA_ALIGNMENT ) {
     
    277277      (uint32_t)( (size_t)d_addr + n_bytes -1);
    278278
    279     ARM_CACHE_L1_ERRATA_764369_HANDLER();
     279    arm_cache_l1_errata_764369_handler();
    280280   
    281281    /* Back starting address up to start of a line and invalidate until end */
     
    302302      (uint32_t)( (size_t)i_addr + n_bytes -1);
    303303
    304     arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_INSTRUCTION );
    305 
    306     ARM_CACHE_L1_ERRATA_764369_HANDLER();
     304    arm_cache_l1_errata_764369_handler();
    307305
    308306    /* Back starting address up to start of a line and invalidate until end */
     
    315313    /* Wait for L1 invalidate to complete */
    316314    _ARM_Data_synchronization_barrier();
    317 
    318     arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_DATA );
    319315  }
    320316}
     
    376372static inline size_t arm_cache_l1_get_data_cache_size( void )
    377373{
     374  rtems_interrupt_level level;
    378375  size_t   size;
    379376  uint32_t line_size     = 0;
    380377  uint32_t associativity = 0;
    381378  uint32_t num_sets      = 0;
     379
     380  rtems_interrupt_disable(level);
     381
     382  arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_DATA );
    382383  arm_cache_l1_properties( &line_size, &associativity,
    383384                           &num_sets );
    384385
     386  rtems_interrupt_enable(level);
     387
    385388  size = (1 << line_size) * associativity * num_sets;
    386389
     
    390393static inline size_t arm_cache_l1_get_instruction_cache_size( void )
    391394{
     395  rtems_interrupt_level level;
    392396  size_t   size;
    393397  uint32_t line_size     = 0;
     
    395399  uint32_t num_sets      = 0;
    396400
     401  rtems_interrupt_disable(level);
     402
    397403  arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_INSTRUCTION );
    398  
    399404  arm_cache_l1_properties( &line_size, &associativity,
    400405                           &num_sets );
    401  
    402   arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_DATA );
     406
     407  rtems_interrupt_enable(level);
    403408
    404409  size = (1 << line_size) * associativity * num_sets;
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