Changeset 5f4f828 in rtems
- Timestamp:
- 11/19/14 13:55:53 (9 years ago)
- Branches:
- 4.11, 5, master
- Children:
- d1eb7b1
- Parents:
- e492e7f8
- git-author:
- Sebastian Huber <sebastian.huber@…> (11/19/14 13:55:53)
- git-committer:
- Sebastian Huber <sebastian.huber@…> (11/20/14 09:30:28)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h
re492e7f8 r5f4f828 26 26 #define LIBBSP_ARM_SHARED_CACHE_L1_H 27 27 28 #include <assert.h>29 28 #include <bsp.h> 30 29 #include <libcpu/arm-cp15.h> … … 47 46 48 47 /* Errata Handlers */ 49 #define ARM_CACHE_L1_ERRATA_764369_HANDLER() \ 50 if( arm_errata_is_applicable_processor_errata_764369() ) { \ 51 _ARM_Data_synchronization_barrier(); \ 52 } 53 54 48 static void arm_cache_l1_errata_764369_handler( void ) 49 { 50 #ifdef RTEMS_SMP 51 _ARM_Data_synchronization_barrier(); 52 #endif 53 } 54 55 55 static void arm_cache_l1_select( const uint32_t selection ) 56 56 { … … 224 224 (uint32_t)( (size_t) d_addr + n_bytes - 1 ); 225 225 226 ARM_CACHE_L1_ERRATA_764369_HANDLER();226 arm_cache_l1_errata_764369_handler(); 227 227 228 228 for (; adx <= ADDR_LAST; adx += ARM_CACHE_L1_CPU_DATA_ALIGNMENT ) { … … 277 277 (uint32_t)( (size_t)d_addr + n_bytes -1); 278 278 279 ARM_CACHE_L1_ERRATA_764369_HANDLER();279 arm_cache_l1_errata_764369_handler(); 280 280 281 281 /* Back starting address up to start of a line and invalidate until end */ … … 302 302 (uint32_t)( (size_t)i_addr + n_bytes -1); 303 303 304 arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_INSTRUCTION ); 305 306 ARM_CACHE_L1_ERRATA_764369_HANDLER(); 304 arm_cache_l1_errata_764369_handler(); 307 305 308 306 /* Back starting address up to start of a line and invalidate until end */ … … 315 313 /* Wait for L1 invalidate to complete */ 316 314 _ARM_Data_synchronization_barrier(); 317 318 arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_DATA );319 315 } 320 316 } … … 376 372 static inline size_t arm_cache_l1_get_data_cache_size( void ) 377 373 { 374 rtems_interrupt_level level; 378 375 size_t size; 379 376 uint32_t line_size = 0; 380 377 uint32_t associativity = 0; 381 378 uint32_t num_sets = 0; 379 380 rtems_interrupt_disable(level); 381 382 arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_DATA ); 382 383 arm_cache_l1_properties( &line_size, &associativity, 383 384 &num_sets ); 384 385 386 rtems_interrupt_enable(level); 387 385 388 size = (1 << line_size) * associativity * num_sets; 386 389 … … 390 393 static inline size_t arm_cache_l1_get_instruction_cache_size( void ) 391 394 { 395 rtems_interrupt_level level; 392 396 size_t size; 393 397 uint32_t line_size = 0; … … 395 399 uint32_t num_sets = 0; 396 400 401 rtems_interrupt_disable(level); 402 397 403 arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_INSTRUCTION ); 398 399 404 arm_cache_l1_properties( &line_size, &associativity, 400 405 &num_sets ); 401 402 arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_DATA);406 407 rtems_interrupt_enable(level); 403 408 404 409 size = (1 << line_size) * associativity * num_sets;
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