Index: c/src/lib/libbsp/m68k/dmv152/startup/bspstart.c
===================================================================
--- c/src/lib/libbsp/m68k/dmv152/startup/bspstart.c	(revision 9b05600b2cc0407688548fe479fecb7ebfb5bbee)
+++ c/src/lib/libbsp/m68k/dmv152/startup/bspstart.c	(revision 5e77d12951fa5ce199fecebd56650558313c8aad)
@@ -85,5 +85,5 @@
    */
 
-  m68k_enable_caching();
+  rtems_cache_enable_instruction();
 
   /*
Index: c/src/lib/libbsp/m68k/idp/startup/bspstart.c
===================================================================
--- c/src/lib/libbsp/m68k/idp/startup/bspstart.c	(revision 9b05600b2cc0407688548fe479fecb7ebfb5bbee)
+++ c/src/lib/libbsp/m68k/idp/startup/bspstart.c	(revision 5e77d12951fa5ce199fecebd56650558313c8aad)
@@ -91,5 +91,5 @@
   m68k_set_vbr( &M68Kvec );
 
-  m68k_enable_caching();
+  rtems_cache_enable_instruction();
 
   /*
Index: c/src/lib/libbsp/m68k/mvme136/startup/bspstart.c
===================================================================
--- c/src/lib/libbsp/m68k/mvme136/startup/bspstart.c	(revision 9b05600b2cc0407688548fe479fecb7ebfb5bbee)
+++ c/src/lib/libbsp/m68k/mvme136/startup/bspstart.c	(revision 5e77d12951fa5ce199fecebd56650558313c8aad)
@@ -74,5 +74,5 @@
   (*(rtems_unsigned8 *)0xfffb0067) = 0x7f; /* make VME access round-robin */
 
-  m68k_enable_caching();
+  rtems_cache_enable_instruction();
 
   /*
Index: c/src/lib/libbsp/m68k/mvme147/startup/bspstart.c
===================================================================
--- c/src/lib/libbsp/m68k/mvme147/startup/bspstart.c	(revision 9b05600b2cc0407688548fe479fecb7ebfb5bbee)
+++ c/src/lib/libbsp/m68k/mvme147/startup/bspstart.c	(revision 5e77d12951fa5ce199fecebd56650558313c8aad)
@@ -80,5 +80,5 @@
       /* make VME access round-robin */
 
-  m68k_enable_caching();
+  rtems_cache_enable_instruction();
 
   /*
Index: c/src/lib/libbsp/m68k/mvme147s/startup/bspstart.c
===================================================================
--- c/src/lib/libbsp/m68k/mvme147s/startup/bspstart.c	(revision 9b05600b2cc0407688548fe479fecb7ebfb5bbee)
+++ c/src/lib/libbsp/m68k/mvme147s/startup/bspstart.c	(revision 5e77d12951fa5ce199fecebd56650558313c8aad)
@@ -140,5 +140,5 @@
   /* Disable D32 transfers : they don't work on my VMEbus rack */
 
-  m68k_enable_caching();
+  rtems_cache_enable_instruction();
 
   /*
Index: c/src/lib/libbsp/powerpc/mbx8xx/network/network.c
===================================================================
--- c/src/lib/libbsp/powerpc/mbx8xx/network/network.c	(revision 9b05600b2cc0407688548fe479fecb7ebfb5bbee)
+++ c/src/lib/libbsp/powerpc/mbx8xx/network/network.c	(revision 5e77d12951fa5ce199fecebd56650558313c8aad)
@@ -747,5 +747,5 @@
 			 * Invalidate the buffer for this descriptor
 			 */
-			rtems_invalidate_multiple_data_cache_lines(rxBd->buffer, rxBd->length);
+			rtems_cache_invalidate_multiple_data_lines(rxBd->buffer, rxBd->length);
       
       m = sc->rxMbuf[rxBdIndex];
@@ -883,5 +883,5 @@
 			 * Invalidate the buffer for this descriptor
 			 */
-			rtems_invalidate_multiple_data_cache_lines(rxBd->buffer, rxBd->length);
+			rtems_cache_invalidate_multiple_data_lines(rxBd->buffer, rxBd->length);
       
       m = sc->rxMbuf[rxBdIndex];
@@ -1023,5 +1023,5 @@
        * Flush the buffer for this descriptor
        */
-      rtems_flush_multiple_data_cache_lines(txBd->buffer, txBd->length);
+      rtems_cache_flush_multiple_data_lines(txBd->buffer, txBd->length);
       
       sc->txMbuf[sc->txBdHead] = m;
@@ -1151,5 +1151,5 @@
        * Flush the buffer for this descriptor
        */
-      rtems_flush_multiple_data_cache_lines(txBd->buffer, txBd->length);
+      rtems_cache_flush_multiple_data_lines(txBd->buffer, txBd->length);
       
       sc->txMbuf[sc->txBdHead] = m;
Index: c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c
===================================================================
--- c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c	(revision 9b05600b2cc0407688548fe479fecb7ebfb5bbee)
+++ c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c	(revision 5e77d12951fa5ce199fecebd56650558313c8aad)
@@ -137,9 +137,9 @@
    */
   #ifdef INSTRUCTION_CACHE_ENABLE
-	rtems_enable_inst_cache();
+	rtems_cache_enable_instruction();
   #endif
 
   #ifdef DATA_CACHE_ENABLE
-	rtems_enable_data_cache();
+	rtems_cache_enable_data();
   #endif
    
Index: c/src/lib/libcpu/i386/cache.c
===================================================================
--- c/src/lib/libcpu/i386/cache.c	(revision 9b05600b2cc0407688548fe479fecb7ebfb5bbee)
+++ c/src/lib/libcpu/i386/cache.c	(revision 5e77d12951fa5ce199fecebd56650558313c8aad)
@@ -16,5 +16,5 @@
   regCr0.cr0.no_write_through = 1;
   i386_set_cr0( regCr0.i );
-  rtems_flush_entire_data_cache();
+  rtems_cache_flush_entire_data();
 }
 
@@ -30,5 +30,5 @@
   regCr0.cr0.no_write_through = 0;
   i386_set_cr0( regCr0.i );
-  /*rtems_flush_entire_data_cache();*/
+  /*rtems_cache_flush_entire_data();*/
 }
 
@@ -39,54 +39,47 @@
  * it does nothing by default.
  *
- * FIXME: Definitions for I386_CACHE_ALIGNMENT are missing above for
- *        each CPU. The routines below should be implemented per CPU,
+ * FIXME: The routines below should be implemented per CPU,
  *        to accomodate the capabilities of each.
  */
 
-/* FIXME: I don't belong here. */
-#define I386_CACHE_ALIGNMENT 16
+#if defined(I386_CACHE_ALIGNMENT)
+void _CPU_cache_flush_1_data_line(const void *d_addr) {}
+void _CPU_cache_invalidate_1_data_line(const void *d_addr) {}
+void _CPU_cache_freeze_data(void) {}
+void _CPU_cache_unfreeze_data(void) {}
+void _CPU_cache_invalidate_1_instruction_line ( const void *d_addr ) {}
+void _CPU_cache_freeze_instruction(void) {}
+void _CPU_cache_unfreeze_instruction(void) {}
 
-#if defined(I386_CACHE_ALIGNMENT)
-#define _CPU_DATA_CACHE_ALIGNMENT I386_CACHE_ALIGNMENT
-#define _CPU_INST_CACHE_ALIGNEMNT I386_CACHE_ALIGNMENT
-
-void _CPU_flush_1_data_cache_line(const void *d_addr) {}
-void _CPU_invalidate_1_data_cache_line(const void *d_addr) {}
-void _CPU_freeze_data_cache(void) {}
-void _CPU_unfreeze_data_cache(void) {}
-void _CPU_invalidate_1_inst_cache_line ( const void *d_addr ) {}
-void _CPU_freeze_inst_cache(void) {}
-void _CPU_unfreeze_inst_cache(void) {}
-
-void _CPU_flush_entire_data_cache(void)
+void _CPU_cache_flush_entire_data(void)
 {
   asm volatile ("wbinvd");
 }
-void _CPU_invalidate_entire_data_cache(void)
+void _CPU_cache_invalidate_entire_data(void)
 {
   asm volatile ("invd");
 }
 
-void _CPU_enable_data_cache(void)
+void _CPU_cache_enable_data(void)
 {
         _CPU_enable_cache();
 }
 
-void _CPU_disable_data_cache(void)
+void _CPU_cache_disable_data(void)
 {
         _CPU_disable_cache();
 }
 
-void _CPU_invalidate_entire_inst_cache(void)
+void _CPU_cache_invalidate_entire_instruction(void)
 {
   asm volatile ("invd");
 }
 
-void _CPU_enable_inst_cache(void)
+void _CPU_cache_enable_instruction(void)
 {
   _CPU_enable_cache();
 }
 
-void _CPU_disable_inst_cache( void )
+void _CPU_cache_disable_instruction( void )
 {
   _CPU_disable_cache();
Index: c/src/lib/libcpu/i386/cache_.h
===================================================================
--- c/src/lib/libcpu/i386/cache_.h	(revision 9b05600b2cc0407688548fe479fecb7ebfb5bbee)
+++ c/src/lib/libcpu/i386/cache_.h	(revision 5e77d12951fa5ce199fecebd56650558313c8aad)
@@ -7,6 +7,6 @@
 
 #define I386_CACHE_ALIGNMENT 16
-#define _CPU_DATA_CACHE_ALIGNMENT I386_CACHE_ALIGNMENT
-#define _CPU_INST_CACHE_ALIGNEMNT I386_CACHE_ALIGNMENT
+#define CPU_DATA_CACHE_ALIGNMENT I386_CACHE_ALIGNMENT
+#define CPU_INSTRUCTION_CACHE_ALIGNEMNT I386_CACHE_ALIGNMENT
 
 #include <libcpu/cache.h>
Index: c/src/lib/libcpu/i386/page.c
===================================================================
--- c/src/lib/libcpu/i386/page.c	(revision 9b05600b2cc0407688548fe479fecb7ebfb5bbee)
+++ c/src/lib/libcpu/i386/page.c	(revision 5e77d12951fa5ce199fecebd56650558313c8aad)
@@ -46,5 +46,5 @@
   cr0 regCr0;
 
-  rtems_flush_entire_data_cache();
+  rtems_cache_flush_entire_data();
   regCr0.i = i386_get_cr0();
   regCr0.cr0.paging = 0;
@@ -61,5 +61,5 @@
   regCr0.cr0.paging = 1;
   i386_set_cr0( regCr0.i );
-  rtems_flush_entire_data_cache();
+  rtems_cache_flush_entire_data();
 }
 
Index: c/src/lib/libcpu/m68k/shared/cache/cache.c
===================================================================
--- c/src/lib/libcpu/m68k/shared/cache/cache.c	(revision 9b05600b2cc0407688548fe479fecb7ebfb5bbee)
+++ c/src/lib/libcpu/m68k/shared/cache/cache.c	(revision 5e77d12951fa5ce199fecebd56650558313c8aad)
@@ -53,8 +53,8 @@
 /* Only the mc68030 has a data cache; it is writethrough only. */
 
-void _CPU_flush_1_data_cache_line ( const void * d_addr ) {}
-void _CPU_flush_entire_data_cache ( const void * d_addr ) {}
+void _CPU_cache_flush_1_data_line ( const void * d_addr ) {}
+void _CPU_cache_flush_entire_data ( const void * d_addr ) {}
 
-void _CPU_invalidate_1_data_cache_line (
+void _CPU_cache_invalidate_1_data_line (
   const void * d_addr )
 {
@@ -64,24 +64,24 @@
 }
 
-void _CPU_invalidate_entire_data_cache ( void )
+void _CPU_cache_invalidate_entire_data ( void )
 {
   _CPU_CACR_OR( 0x00000800 );
 }
 
-void _CPU_freeze_data_cache ( void )
+void _CPU_cache_freeze_data ( void )
 {
   _CPU_CACR_OR( 0x00000200 );
 }
 
-void _CPU_unfreeze_data_cache ( void )
+void _CPU_cache_unfreeze_data ( void )
 {
   _CPU_CACR_AND( 0xFFFFFDFF );
 }
 
-void _CPU_enable_data_cache ( void )
+void _CPU_cache_enable_data ( void )
 {
   _CPU_CACR_OR( 0x00000100 );
 }
-void _CPU_disable_data_cache (	void )
+void _CPU_cache_disable_data (	void )
 {
   _CPU_CACR_AND( 0xFFFFFEFF );
@@ -92,5 +92,5 @@
 /* Both the 68020 and 68030 have instruction caches */
 
-void _CPU_invalidate_1_inst_cache_line (
+void _CPU_cache_invalidate_1_instruction_line (
   const void * d_addr )
 {
@@ -100,25 +100,25 @@
 }
 
-void _CPU_invalidate_entire_inst_cache ( void )
+void _CPU_cache_invalidate_entire_instruction ( void )
 {
   _CPU_CACR_OR( 0x00000008 );
 }
 
-void _CPU_freeze_inst_cache ( void )
+void _CPU_cache_freeze_instruction ( void )
 {
   _CPU_CACR_OR( 0x00000002);
 }
 
-void _CPU_unfreeze_inst_cache ( void )
+void _CPU_cache_unfreeze_instruction ( void )
 {
   _CPU_CACR_AND( 0xFFFFFFFD );
 }
 
-void _CPU_enable_inst_cache ( void )
+void _CPU_cache_enable_instruction ( void )
 {
   _CPU_CACR_OR( 0x00000001 );
 }
 
-void _CPU_disable_inst_cache (	void )
+void _CPU_cache_disable_instruction (	void )
 {
   _CPU_CACR_AND( 0xFFFFFFFE );
@@ -129,10 +129,10 @@
 
 /* Cannot be frozen */
-void _CPU_freeze_data_cache ( void ) {}
-void _CPU_unfreeze_data_cache ( void ) {}
-void _CPU_freeze_inst_cache ( void ) {}
-void _CPU_unfreeze_inst_cache ( void ) {}
+void _CPU_cache_freeze_data ( void ) {}
+void _CPU_cache_unfreeze_data ( void ) {}
+void _CPU_cache_freeze_instruction ( void ) {}
+void _CPU_cache_unfreeze_instruction ( void ) {}
 
-void _CPU_flush_1_data_cache_line (
+void _CPU_cache_flush_1_data_line (
   const void * d_addr )
 {
@@ -141,5 +141,5 @@
 }
 
-void _CPU_invalidate_1_data_cache_line (
+void _CPU_cache_invalidate_1_data_line (
   const void * d_addr )
 {
@@ -148,25 +148,25 @@
 }
 
-void _CPU_flush_entire_data_cache ( void )
+void _CPU_cache_flush_entire_data ( void )
 {
 	asm volatile ( "cpusha %%dc" :: );
 }
 
-void _CPU_invalidate_entire_data_cache ( void )
+void _CPU_cache_invalidate_entire_data ( void )
 {
 	asm volatile ( "cinva %%dc" :: );
 }
 
-void _CPU_enable_data_cache ( void )
+void _CPU_cache_enable_data ( void )
 {
   _CPU_CACR_OR( 0x80000000 );
 }
 
-void _CPU_disable_data_cache ( void )
+void _CPU_cache_disable_data ( void )
 {
   _CPU_CACR_AND( 0x7FFFFFFF );
 }
 
-void _CPU_invalidate_1_inst_cache_line (
+void _CPU_cache_invalidate_1_instruction_line (
   const void * i_addr )
 {
@@ -175,15 +175,15 @@
 }
 
-void _CPU_invalidate_entire_inst_cache ( void )
+void _CPU_cache_invalidate_entire_instruction ( void )
 {
 		asm volatile ( "cinva %%ic" :: );
 }
 
-void _CPU_enable_inst_cache ( void )
+void _CPU_cache_enable_instruction ( void )
 {
   _CPU_CACR_OR( 0x00008000 );
 }
 
-void _CPU_disable_inst_cache ( void )
+void _CPU_cache_disable_instruction ( void )
 {
 	_CPU_CACR_AND( 0xFFFF7FFF );
Index: c/src/lib/libcpu/m68k/shared/cache/cache_.h
===================================================================
--- c/src/lib/libcpu/m68k/shared/cache/cache_.h	(revision 9b05600b2cc0407688548fe479fecb7ebfb5bbee)
+++ c/src/lib/libcpu/m68k/shared/cache/cache_.h	(revision 5e77d12951fa5ce199fecebd56650558313c8aad)
@@ -7,19 +7,19 @@
 
 #if defined(__mc68020__)
-#define M68K_INST_CACHE_ALIGNMENT 16
+#define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
 #elif defined(__mc68030__)
-#define M68K_INST_CACHE_ALIGNMENT 16
+#define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
 #define M68K_DATA_CACHE_ALIGNMENT 16
 #elif ( defined(__mc68040__) || defined (__mc68060__) )
-#define M68K_INST_CACHE_ALIGNMENT 16
+#define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
 #define M68K_DATA_CACHE_ALIGNMENT 16
 #endif
 
 #if defined(M68K_DATA_CACHE_ALIGNMENT)
-#define _CPU_DATA_CACHE_ALIGNMENT M68K_DATA_CACHE_ALIGNMENT
+#define CPU_DATA_CACHE_ALIGNMENT M68K_DATA_CACHE_ALIGNMENT
 #endif
 
-#if defined(M68K_INST_CACHE_ALIGNMENT)
-#define _CPU_INST_CACHE_ALIGNMENT M68K_INST_CACHE_ALIGNMENT
+#if defined(M68K_INSTRUCTION_CACHE_ALIGNMENT)
+#define CPU_INSTRUCTION_CACHE_ALIGNMENT M68K_INSTRUCTION_CACHE_ALIGNMENT
 #endif
 
Index: c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c	(revision 9b05600b2cc0407688548fe479fecb7ebfb5bbee)
+++ c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c	(revision 5e77d12951fa5ce199fecebd56650558313c8aad)
@@ -400,5 +400,5 @@
     /* Check that the buffer is ours */
     if ((RxBd[SCC2_MINOR]->status & M8xx_BD_EMPTY) == 0) {
-      rtems_invalidate_multiple_data_cache_lines( 
+      rtems_cache_invalidate_multiple_data_lines( 
         (const void *) RxBd[SCC2_MINOR]->buffer, 
         RxBd[SCC2_MINOR]->length );
@@ -443,5 +443,5 @@
     /* Check that the buffer is ours */
     if ((RxBd[SCC3_MINOR]->status & M8xx_BD_EMPTY) == 0) {
-      rtems_invalidate_multiple_data_cache_lines( 
+      rtems_cache_invalidate_multiple_data_lines( 
         (const void *) RxBd[SCC3_MINOR]->buffer, 
         RxBd[SCC3_MINOR]->length );
@@ -485,5 +485,5 @@
     /* Check that the buffer is ours */
     if ((RxBd[SCC4_MINOR]->status & M8xx_BD_EMPTY) == 0) {
-      rtems_invalidate_multiple_data_cache_lines( 
+      rtems_cache_invalidate_multiple_data_lines( 
         (const void *) RxBd[SCC4_MINOR]->buffer, 
         RxBd[SCC4_MINOR]->length );
@@ -527,5 +527,5 @@
     /* Check that the buffer is ours */
     if ((RxBd[SMC1_MINOR]->status & M8xx_BD_EMPTY) == 0) {
-      rtems_invalidate_multiple_data_cache_lines( 
+      rtems_cache_invalidate_multiple_data_lines( 
         (const void *) RxBd[SMC1_MINOR]->buffer, 
         RxBd[SMC1_MINOR]->length );
@@ -569,5 +569,5 @@
     /* Check that the buffer is ours */
     if ((RxBd[SMC2_MINOR]->status & M8xx_BD_EMPTY) == 0) {
-      rtems_invalidate_multiple_data_cache_lines( 
+      rtems_cache_invalidate_multiple_data_lines( 
         (const void *) RxBd[SMC2_MINOR]->buffer, 
         RxBd[SMC2_MINOR]->length );
@@ -985,5 +985,5 @@
     return -1;
   }
-  rtems_invalidate_multiple_data_cache_lines( 
+  rtems_cache_invalidate_multiple_data_lines( 
     (const void *) RxBd[minor]->buffer,
     RxBd[minor]->length
@@ -1005,5 +1005,5 @@
 )
 {
-  rtems_flush_multiple_data_cache_lines( buf, len );
+  rtems_cache_flush_multiple_data_lines( buf, len );
   TxBd[minor]->buffer = (char *) buf;
   TxBd[minor]->length = len;
@@ -1024,5 +1024,5 @@
       continue;
     txBuf[minor] = *buf++;
-    rtems_flush_multiple_data_cache_lines(
+    rtems_cache_flush_multiple_data_lines(
        (const void *) TxBd[minor]->buffer,
        TxBd[minor]->length
Index: c/src/lib/libcpu/powerpc/shared/src/cache.c
===================================================================
--- c/src/lib/libcpu/powerpc/shared/src/cache.c	(revision 9b05600b2cc0407688548fe479fecb7ebfb5bbee)
+++ c/src/lib/libcpu/powerpc/shared/src/cache.c	(revision 5e77d12951fa5ce199fecebd56650558313c8aad)
@@ -43,5 +43,5 @@
   } while (0)
 
-void _CPU_enable_data_cache (
+void _CPU_cache_enable_data (
 	void )
 {
@@ -52,5 +52,5 @@
 }
 
-void _CPU_disable_data_cache (
+void _CPU_cache_disable_data (
 	void )
 {
@@ -61,5 +61,5 @@
 }
 
-void _CPU_enable_inst_cache (
+void _CPU_cache_enable_inst (
 	void )
 {
@@ -70,5 +70,5 @@
 }
 
-void _CPU_disable_inst_cache (
+void _CPU_cache_disable_inst (
 	void )
 {
@@ -86,5 +86,5 @@
   __asm__ volatile ("isync\n"::)
 
-void _CPU_flush_1_data_cache_line(
+void _CPU_cache_flush_1_data_line(
 	const void * _address )
 {
@@ -93,5 +93,5 @@
 }
 
-void _CPU_invalidate_1_data_cache_line(
+void _CPU_cache_invalidate_1_data_line(
 	const void * _address )
 {
@@ -100,10 +100,10 @@
 }
 
-void _CPU_flush_entire_data_cache ( void ) {}
-void _CPU_invalidate_entire_data_cache ( void ) {}
-void _CPU_freeze_data_cache ( void ) {}
-void _CPU_unfreeze_data_cache ( void ) {}
+void _CPU_cache_flush_entire_data ( void ) {}
+void _CPU_cache_invalidate_entire_data ( void ) {}
+void _CPU_cache_freeze_data ( void ) {}
+void _CPU_cache_unfreeze_data ( void ) {}
 
-void _CPU_enable_data_cache ( void )
+void _CPU_cache_enable_data ( void )
 {
   unsigned32 r1;
@@ -113,5 +113,5 @@
 }
 
-void _CPU_disable_data_cache ( void )
+void _CPU_cache_disable_data ( void )
 {
   unsigned32 r1;
@@ -121,5 +121,5 @@
 }
 
-void _CPU_invalidate_1_inst_cache_line(
+void _CPU_cache_invalidate_1_inst_line(
 	const void * _address )
 {
@@ -128,9 +128,9 @@
 }
 
-void _CPU_invalidate_entire_inst_cache ( void ) {}
-void _CPU_freeze_inst_cache ( void ) {}
-void _CPU_unfreeze_inst_cache ( void ) {}
+void _CPU_cache_invalidate_entire_inst ( void ) {}
+void _CPU_cache_freeze_inst ( void ) {}
+void _CPU_cache_unfreeze_inst ( void ) {}
 
-void _CPU_enable_inst_cache ( void )
+void _CPU_cache_enable_inst ( void )
 {
   unsigned32 r1;
@@ -140,5 +140,5 @@
 }
 
-void _CPU_disable_inst_cache ( void )
+void _CPU_cache_disable_inst ( void )
 {
   unsigned32 r1;
Index: c/src/lib/libcpu/powerpc/shared/src/cache_.h
===================================================================
--- c/src/lib/libcpu/powerpc/shared/src/cache_.h	(revision 9b05600b2cc0407688548fe479fecb7ebfb5bbee)
+++ c/src/lib/libcpu/powerpc/shared/src/cache_.h	(revision 5e77d12951fa5ce199fecebd56650558313c8aad)
@@ -16,11 +16,11 @@
 
 #if defined(ppc603)                     /* And possibly others */
-#define _CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
-#define _CPU_INST_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
+#define CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
+#define CPU_INSTRUCTION_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
 
 #elif ( defined(mpc860) || defined(mpc821) )
 
-#define _CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
-#define _CPU_INST_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
+#define CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
+#define CPU_INSTRUCTION_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
 
 #endif
Index: c/src/lib/libcpu/shared/include/cache.h
===================================================================
--- c/src/lib/libcpu/shared/include/cache.h	(revision 9b05600b2cc0407688548fe479fecb7ebfb5bbee)
+++ c/src/lib/libcpu/shared/include/cache.h	(revision 5e77d12951fa5ce199fecebd56650558313c8aad)
@@ -10,22 +10,18 @@
 #include <sys/types.h>
 
-void _CPU_disable_cache();
-void _CPU_enable_cache();
-
-void _CPU_flush_1_data_cache_line(const void *d_addr);
-void _CPU_invalidate_1_data_cache_line(const void *d_addr);
-void _CPU_freeze_data_cache(void);
-void _CPU_unfreeze_data_cache(void);
-void _CPU_invalidate_1_inst_cache_line(const void *d_addr);
-void _CPU_freeze_inst_cache(void);
-void _CPU_unfreeze_inst_cache(void);
-
-void _CPU_flush_entire_data_cache(void);
-void _CPU_invalidate_entire_data_cache(void);
-void _CPU_enable_data_cache(void);
-void _CPU_disable_data_cache(void);
-void _CPU_invalidate_entire_inst_cache(void);
-void _CPU_enable_inst_cache(void);
-void _CPU_disable_inst_cache(void);
+void _CPU_cache_flush_1_data_line(const void *d_addr);
+void _CPU_cache_invalidate_1_data_line(const void *d_addr);
+void _CPU_cache_freeze_data(void);
+void _CPU_cache_unfreeze_data(void);
+void _CPU_cache_invalidate_1_instruction_line(const void *d_addr);
+void _CPU_cache_freeze_instruction(void);
+void _CPU_cache_unfreeze_instruction(void);
+void _CPU_cache_flush_entire_data(void);
+void _CPU_cache_invalidate_entire_data(void);
+void _CPU_cache_enable_data(void);
+void _CPU_cache_disable_data(void);
+void _CPU_cache_invalidate_entire_instruction(void);
+void _CPU_cache_enable_instruction(void);
+void _CPU_cache_disable_instruction(void);
 
 #endif
Index: c/src/lib/libcpu/shared/src/cache_aligned_malloc.c
===================================================================
--- c/src/lib/libcpu/shared/src/cache_aligned_malloc.c	(revision 9b05600b2cc0407688548fe479fecb7ebfb5bbee)
+++ c/src/lib/libcpu/shared/src/cache_aligned_malloc.c	(revision 5e77d12951fa5ce199fecebd56650558313c8aad)
@@ -33,8 +33,8 @@
    * block beyond the header.
    */
-#if defined(_CPU_DATA_CACHE_ALIGNMENT)
+#if defined(CPU_DATA_CACHE_ALIGNMENT)
   return (void *) ((((unsigned long)
-     malloc( nbytes + _CPU_DATA_CACHE_ALIGNMENT - 1 ))
-        + _CPU_DATA_CACHE_ALIGNMENT - 1 ) &(~(_CPU_DATA_CACHE_ALIGNMENT - 1)) );
+     malloc( nbytes + CPU_DATA_CACHE_ALIGNMENT - 1 ))
+        + CPU_DATA_CACHE_ALIGNMENT - 1 ) &(~(CPU_DATA_CACHE_ALIGNMENT - 1)) );
 #else
   return malloc( nbytes );
Index: c/src/lib/libcpu/shared/src/cache_manager.c
===================================================================
--- c/src/lib/libcpu/shared/src/cache_manager.c	(revision 9b05600b2cc0407688548fe479fecb7ebfb5bbee)
+++ c/src/lib/libcpu/shared/src/cache_manager.c	(revision 5e77d12951fa5ce199fecebd56650558313c8aad)
@@ -12,15 +12,16 @@
  *  The functions in this file implement the API to the RTEMS Cache Manager and
  *  are divided into data cache and instruction cache functions. Data cache
- *  functions are only declared if a data cache is supported. Instruction
- *  cache functions are only declared if an instruction cache is supported.
- *  Support for a particular cache exists only if _CPU_x_CACHE_ALIGNMENT is
- *  defined, where x E {DATA, INST}. These definitions are found in the CPU
- *  dependent source files in the supercore, often
- *  
- *  rtems/c/src/exec/score/cpu/CPU/rtems/score/CPU.h
+ *  functions only have bodies if a data cache is supported. Instruction
+ *  cache functions only have bodies if an instruction cache is supported.
+ *  Support for a particular cache exists only if CPU_x_CACHE_ALIGNMENT is
+ *  defined, where x E {DATA, INSTRUCTION}. These definitions are found in
+ *  the Cache Manager Wrapper header files, often
+ *  
+ *  rtems/c/src/lib/libcpu/CPU/cache_.h
  *  
  *  The functions below are implemented with CPU dependent inline routines
- *  also found in the above file. In the event that a CPU does not support a
- *  specific function, the CPU dependent routine does nothing (but does exist).
+ *  found in the cache.c files for each CPU. In the event that a CPU does
+ *  not support a specific function for a cache it has, the CPU dependent
+ *  routine does nothing (but does exist).
  *  
  *  At this point, the Cache Manager makes no considerations, and provides no
@@ -46,7 +47,7 @@
  */
 void
-rtems_flush_multiple_data_cache_lines( const void * d_addr, size_t n_bytes )
-{
-#if defined(_CPU_DATA_CACHE_ALIGNMENT)
+rtems_cache_flush_multiple_data_lines( const void * d_addr, size_t n_bytes )
+{
+#if defined(CPU_DATA_CACHE_ALIGNMENT)
   const void * final_address;
 
@@ -58,8 +59,8 @@
 
   final_address = (void *)((size_t)d_addr + n_bytes - 1);
-  d_addr = (void *)((size_t)d_addr & ~(_CPU_DATA_CACHE_ALIGNMENT - 1));
+  d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1));
   while( d_addr <= final_address )  {
-    _CPU_flush_1_data_cache_line( d_addr );
-    d_addr = (void *)((size_t)d_addr + _CPU_DATA_CACHE_ALIGNMENT);
+    _CPU_cache_flush_1_data_line( d_addr );
+    d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT);
   }
 #endif
@@ -74,7 +75,7 @@
 
 void
-rtems_invalidate_multiple_data_cache_lines( const void * d_addr, size_t n_bytes )
-{
-#if defined(_CPU_DATA_CACHE_ALIGNMENT)
+rtems_cache_invalidate_multiple_data_lines( const void * d_addr, size_t n_bytes )
+{
+#if defined(CPU_DATA_CACHE_ALIGNMENT)
   const void * final_address;
 
@@ -86,8 +87,8 @@
 
   final_address = (void *)((size_t)d_addr + n_bytes - 1);
-  d_addr = (void *)((size_t)d_addr & ~(_CPU_DATA_CACHE_ALIGNMENT - 1));
+  d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1));
   while( final_address > d_addr ) {
-    _CPU_invalidate_1_data_cache_line( d_addr );
-    d_addr = (void *)((size_t)d_addr + _CPU_DATA_CACHE_ALIGNMENT);
+    _CPU_cache_invalidate_1_data_line( d_addr );
+    d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT);
   }
 #endif
@@ -100,11 +101,11 @@
  */
 void
-rtems_flush_entire_data_cache( void )
-{
-#if defined(_CPU_DATA_CACHE_ALIGNMENT)
+rtems_cache_flush_entire_data( void )
+{
+#if defined(CPU_DATA_CACHE_ALIGNMENT)
    /*
     * Call the CPU-specific routine
     */
-   _CPU_flush_entire_data_cache();
+   _CPU_cache_flush_entire_data();
 #endif
 }
@@ -116,12 +117,12 @@
  */
 void
-rtems_invalidate_entire_data_cache( void )
-{
-#if defined(_CPU_DATA_CACHE_ALIGNMENT)
+rtems_cache_invalidate_entire_data( void )
+{
+#if defined(CPU_DATA_CACHE_ALIGNMENT)
  /*
   * Call the CPU-specific routine
   */
 
- _CPU_invalidate_entire_data_cache();
+ _CPU_cache_invalidate_entire_data();
 #endif
 }
@@ -132,8 +133,8 @@
  */
 int
-rtems_get_data_cache_line_size( void )
-{
-#if defined(_CPU_DATA_CACHE_ALIGNMENT)
-  return _CPU_DATA_CACHE_ALIGNMENT;
+rtems_cache_get_data_line_size( void )
+{
+#if defined(CPU_DATA_CACHE_ALIGNMENT)
+  return CPU_DATA_CACHE_ALIGNMENT;
 #else
   return 0;
@@ -147,8 +148,8 @@
  */
 void
-rtems_freeze_data_cache( void )
-{
-#if defined(_CPU_DATA_CACHE_ALIGNMENT)
-  _CPU_freeze_data_cache();
+rtems_cache_freeze_data( void )
+{
+#if defined(CPU_DATA_CACHE_ALIGNMENT)
+  _CPU_cache_freeze_data();
 #endif
 }
@@ -158,8 +159,8 @@
  * This function unfreezes the instruction cache.
  */
-void rtems_unfreeze_data_cache( void )
-{
-#if defined(_CPU_DATA_CACHE_ALIGNMENT)
-  _CPU_unfreeze_data_cache();
+void rtems_cache_unfreeze_data( void )
+{
+#if defined(CPU_DATA_CACHE_ALIGNMENT)
+  _CPU_cache_unfreeze_data();
 #endif
 }
@@ -168,8 +169,8 @@
 /* Turn on the data cache. */
 void
-rtems_enable_data_cache( void )
-{
-#if defined(_CPU_DATA_CACHE_ALIGNMENT)
-  _CPU_enable_data_cache();
+rtems_cache_enable_data( void )
+{
+#if defined(CPU_DATA_CACHE_ALIGNMENT)
+  _CPU_cache_enable_data();
 #endif
 }
@@ -178,8 +179,8 @@
 /* Turn off the data cache. */
 void
-rtems_disable_data_cache( void )
-{
-#if defined(_CPU_DATA_CACHE_ALIGNMENT)
-  _CPU_disable_data_cache();
+rtems_cache_disable_data( void )
+{
+#if defined(CPU_DATA_CACHE_ALIGNMENT)
+  _CPU_cache_disable_data();
 #endif
 }
@@ -197,7 +198,7 @@
  */
 void
-rtems_invalidate_multiple_inst_cache_lines( const void * i_addr, size_t n_bytes )
-{
-#if defined(_CPU_INST_CACHE_ALIGNMENT)
+rtems_cache_invalidate_multiple_instruction_lines( const void * i_addr, size_t n_bytes )
+{
+#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
   const void * final_address;
 
@@ -209,8 +210,8 @@
 
   final_address = (void *)((size_t)i_addr + n_bytes - 1);
-  i_addr = (void *)((size_t)i_addr & ~(_CPU_INST_CACHE_ALIGNMENT - 1));
+  i_addr = (void *)((size_t)i_addr & ~(CPU_INSTRUCTION_CACHE_ALIGNMENT - 1));
   while( final_address > i_addr ) {
-    _CPU_invalidate_1_inst_cache_line( i_addr );
-    i_addr = (void *)((size_t)i_addr + _CPU_INST_CACHE_ALIGNMENT);
+    _CPU_cache_invalidate_1_instruction_line( i_addr );
+    i_addr = (void *)((size_t)i_addr + CPU_INSTRUCTION_CACHE_ALIGNMENT);
   }
 #endif
@@ -223,12 +224,12 @@
  */
 void
-rtems_invalidate_entire_inst_cache( void )
-{
-#if defined(_CPU_INST_CACHE_ALIGNMENT)
+rtems_cache_invalidate_entire_instruction( void )
+{
+#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
  /*
   * Call the CPU-specific routine
   */
 
- _CPU_invalidate_entire_inst_cache();
+ _CPU_cache_invalidate_entire_instruction();
 #endif
 }
@@ -239,8 +240,8 @@
  */
 int
-rtems_get_inst_cache_line_size( void )
-{
-#if defined(_CPU_INST_CACHE_ALIGNMENT)
-  return _CPU_INST_CACHE_ALIGNMENT;
+rtems_cache_get_instruction_line_size( void )
+{
+#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
+  return CPU_INSTRUCTION_CACHE_ALIGNMENT;
 #else
   return 0;
@@ -254,8 +255,8 @@
  */
 void
-rtems_freeze_inst_cache( void )
-{
-#if defined(_CPU_INST_CACHE_ALIGNMENT)
-  _CPU_freeze_inst_cache();
+rtems_cache_freeze_instruction( void )
+{
+#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
+  _CPU_cache_freeze_instruction();
 #endif
 }
@@ -265,8 +266,8 @@
  * This function unfreezes the instruction cache.
  */
-void rtems_unfreeze_inst_cache( void )
-{
-#if defined(_CPU_INST_CACHE_ALIGNMENT)
-  _CPU_unfreeze_inst_cache();
+void rtems_cache_unfreeze_instruction( void )
+{
+#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
+  _CPU_cache_unfreeze_instruction();
 #endif
 }
@@ -275,8 +276,8 @@
 /* Turn on the instruction cache. */
 void
-rtems_enable_inst_cache( void )
-{
-#if defined(_CPU_INST_CACHE_ALIGNMENT)
-  _CPU_enable_inst_cache();
+rtems_cache_enable_instruction( void )
+{
+#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
+  _CPU_cache_enable_instruction();
 #endif
 }
@@ -285,8 +286,8 @@
 /* Turn off the instruction cache. */
 void
-rtems_disable_inst_cache( void )
-{
-#if defined(_CPU_INST_CACHE_ALIGNMENT)
-  _CPU_disable_inst_cache();
-#endif
-}
+rtems_cache_disable_instruction( void )
+{
+#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
+  _CPU_cache_disable_instruction();
+#endif
+}
