Changeset 5e77d129 in rtems for c/src/lib/libcpu/shared/src


Ignore:
Timestamp:
Jun 14, 2000, 8:32:44 PM (20 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
b91b1cf
Parents:
9b05600
Message:

Patch from John Cotton <john.cotton@…> to correct cache
routine naming to follow RTEMS package/object.method rule.
This patch also eliminated calls to the obsolete routine
m68k_enable_caching.

Location:
c/src/lib/libcpu/shared/src
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/shared/src/cache_aligned_malloc.c

    r9b05600 r5e77d129  
    3333   * block beyond the header.
    3434   */
    35 #if defined(_CPU_DATA_CACHE_ALIGNMENT)
     35#if defined(CPU_DATA_CACHE_ALIGNMENT)
    3636  return (void *) ((((unsigned long)
    37      malloc( nbytes + _CPU_DATA_CACHE_ALIGNMENT - 1 ))
    38         + _CPU_DATA_CACHE_ALIGNMENT - 1 ) &(~(_CPU_DATA_CACHE_ALIGNMENT - 1)) );
     37     malloc( nbytes + CPU_DATA_CACHE_ALIGNMENT - 1 ))
     38        + CPU_DATA_CACHE_ALIGNMENT - 1 ) &(~(CPU_DATA_CACHE_ALIGNMENT - 1)) );
    3939#else
    4040  return malloc( nbytes );
  • c/src/lib/libcpu/shared/src/cache_manager.c

    r9b05600 r5e77d129  
    1212 *  The functions in this file implement the API to the RTEMS Cache Manager and
    1313 *  are divided into data cache and instruction cache functions. Data cache
    14  *  functions are only declared if a data cache is supported. Instruction
    15  *  cache functions are only declared if an instruction cache is supported.
    16  *  Support for a particular cache exists only if _CPU_x_CACHE_ALIGNMENT is
    17  *  defined, where x E {DATA, INST}. These definitions are found in the CPU
    18  *  dependent source files in the supercore, often
    19  * 
    20  *  rtems/c/src/exec/score/cpu/CPU/rtems/score/CPU.h
     14 *  functions only have bodies if a data cache is supported. Instruction
     15 *  cache functions only have bodies if an instruction cache is supported.
     16 *  Support for a particular cache exists only if CPU_x_CACHE_ALIGNMENT is
     17 *  defined, where x E {DATA, INSTRUCTION}. These definitions are found in
     18 *  the Cache Manager Wrapper header files, often
     19 * 
     20 *  rtems/c/src/lib/libcpu/CPU/cache_.h
    2121 * 
    2222 *  The functions below are implemented with CPU dependent inline routines
    23  *  also found in the above file. In the event that a CPU does not support a
    24  *  specific function, the CPU dependent routine does nothing (but does exist).
     23 *  found in the cache.c files for each CPU. In the event that a CPU does
     24 *  not support a specific function for a cache it has, the CPU dependent
     25 *  routine does nothing (but does exist).
    2526 * 
    2627 *  At this point, the Cache Manager makes no considerations, and provides no
     
    4647 */
    4748void
    48 rtems_flush_multiple_data_cache_lines( const void * d_addr, size_t n_bytes )
    49 {
    50 #if defined(_CPU_DATA_CACHE_ALIGNMENT)
     49rtems_cache_flush_multiple_data_lines( const void * d_addr, size_t n_bytes )
     50{
     51#if defined(CPU_DATA_CACHE_ALIGNMENT)
    5152  const void * final_address;
    5253
     
    5859
    5960  final_address = (void *)((size_t)d_addr + n_bytes - 1);
    60   d_addr = (void *)((size_t)d_addr & ~(_CPU_DATA_CACHE_ALIGNMENT - 1));
     61  d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1));
    6162  while( d_addr <= final_address )  {
    62     _CPU_flush_1_data_cache_line( d_addr );
    63     d_addr = (void *)((size_t)d_addr + _CPU_DATA_CACHE_ALIGNMENT);
     63    _CPU_cache_flush_1_data_line( d_addr );
     64    d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT);
    6465  }
    6566#endif
     
    7475
    7576void
    76 rtems_invalidate_multiple_data_cache_lines( const void * d_addr, size_t n_bytes )
    77 {
    78 #if defined(_CPU_DATA_CACHE_ALIGNMENT)
     77rtems_cache_invalidate_multiple_data_lines( const void * d_addr, size_t n_bytes )
     78{
     79#if defined(CPU_DATA_CACHE_ALIGNMENT)
    7980  const void * final_address;
    8081
     
    8687
    8788  final_address = (void *)((size_t)d_addr + n_bytes - 1);
    88   d_addr = (void *)((size_t)d_addr & ~(_CPU_DATA_CACHE_ALIGNMENT - 1));
     89  d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1));
    8990  while( final_address > d_addr ) {
    90     _CPU_invalidate_1_data_cache_line( d_addr );
    91     d_addr = (void *)((size_t)d_addr + _CPU_DATA_CACHE_ALIGNMENT);
     91    _CPU_cache_invalidate_1_data_line( d_addr );
     92    d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT);
    9293  }
    9394#endif
     
    100101 */
    101102void
    102 rtems_flush_entire_data_cache( void )
    103 {
    104 #if defined(_CPU_DATA_CACHE_ALIGNMENT)
     103rtems_cache_flush_entire_data( void )
     104{
     105#if defined(CPU_DATA_CACHE_ALIGNMENT)
    105106   /*
    106107    * Call the CPU-specific routine
    107108    */
    108    _CPU_flush_entire_data_cache();
     109   _CPU_cache_flush_entire_data();
    109110#endif
    110111}
     
    116117 */
    117118void
    118 rtems_invalidate_entire_data_cache( void )
    119 {
    120 #if defined(_CPU_DATA_CACHE_ALIGNMENT)
     119rtems_cache_invalidate_entire_data( void )
     120{
     121#if defined(CPU_DATA_CACHE_ALIGNMENT)
    121122 /*
    122123  * Call the CPU-specific routine
    123124  */
    124125
    125  _CPU_invalidate_entire_data_cache();
     126 _CPU_cache_invalidate_entire_data();
    126127#endif
    127128}
     
    132133 */
    133134int
    134 rtems_get_data_cache_line_size( void )
    135 {
    136 #if defined(_CPU_DATA_CACHE_ALIGNMENT)
    137   return _CPU_DATA_CACHE_ALIGNMENT;
     135rtems_cache_get_data_line_size( void )
     136{
     137#if defined(CPU_DATA_CACHE_ALIGNMENT)
     138  return CPU_DATA_CACHE_ALIGNMENT;
    138139#else
    139140  return 0;
     
    147148 */
    148149void
    149 rtems_freeze_data_cache( void )
    150 {
    151 #if defined(_CPU_DATA_CACHE_ALIGNMENT)
    152   _CPU_freeze_data_cache();
     150rtems_cache_freeze_data( void )
     151{
     152#if defined(CPU_DATA_CACHE_ALIGNMENT)
     153  _CPU_cache_freeze_data();
    153154#endif
    154155}
     
    158159 * This function unfreezes the instruction cache.
    159160 */
    160 void rtems_unfreeze_data_cache( void )
    161 {
    162 #if defined(_CPU_DATA_CACHE_ALIGNMENT)
    163   _CPU_unfreeze_data_cache();
     161void rtems_cache_unfreeze_data( void )
     162{
     163#if defined(CPU_DATA_CACHE_ALIGNMENT)
     164  _CPU_cache_unfreeze_data();
    164165#endif
    165166}
     
    168169/* Turn on the data cache. */
    169170void
    170 rtems_enable_data_cache( void )
    171 {
    172 #if defined(_CPU_DATA_CACHE_ALIGNMENT)
    173   _CPU_enable_data_cache();
     171rtems_cache_enable_data( void )
     172{
     173#if defined(CPU_DATA_CACHE_ALIGNMENT)
     174  _CPU_cache_enable_data();
    174175#endif
    175176}
     
    178179/* Turn off the data cache. */
    179180void
    180 rtems_disable_data_cache( void )
    181 {
    182 #if defined(_CPU_DATA_CACHE_ALIGNMENT)
    183   _CPU_disable_data_cache();
     181rtems_cache_disable_data( void )
     182{
     183#if defined(CPU_DATA_CACHE_ALIGNMENT)
     184  _CPU_cache_disable_data();
    184185#endif
    185186}
     
    197198 */
    198199void
    199 rtems_invalidate_multiple_inst_cache_lines( const void * i_addr, size_t n_bytes )
    200 {
    201 #if defined(_CPU_INST_CACHE_ALIGNMENT)
     200rtems_cache_invalidate_multiple_instruction_lines( const void * i_addr, size_t n_bytes )
     201{
     202#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
    202203  const void * final_address;
    203204
     
    209210
    210211  final_address = (void *)((size_t)i_addr + n_bytes - 1);
    211   i_addr = (void *)((size_t)i_addr & ~(_CPU_INST_CACHE_ALIGNMENT - 1));
     212  i_addr = (void *)((size_t)i_addr & ~(CPU_INSTRUCTION_CACHE_ALIGNMENT - 1));
    212213  while( final_address > i_addr ) {
    213     _CPU_invalidate_1_inst_cache_line( i_addr );
    214     i_addr = (void *)((size_t)i_addr + _CPU_INST_CACHE_ALIGNMENT);
     214    _CPU_cache_invalidate_1_instruction_line( i_addr );
     215    i_addr = (void *)((size_t)i_addr + CPU_INSTRUCTION_CACHE_ALIGNMENT);
    215216  }
    216217#endif
     
    223224 */
    224225void
    225 rtems_invalidate_entire_inst_cache( void )
    226 {
    227 #if defined(_CPU_INST_CACHE_ALIGNMENT)
     226rtems_cache_invalidate_entire_instruction( void )
     227{
     228#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
    228229 /*
    229230  * Call the CPU-specific routine
    230231  */
    231232
    232  _CPU_invalidate_entire_inst_cache();
     233 _CPU_cache_invalidate_entire_instruction();
    233234#endif
    234235}
     
    239240 */
    240241int
    241 rtems_get_inst_cache_line_size( void )
    242 {
    243 #if defined(_CPU_INST_CACHE_ALIGNMENT)
    244   return _CPU_INST_CACHE_ALIGNMENT;
     242rtems_cache_get_instruction_line_size( void )
     243{
     244#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
     245  return CPU_INSTRUCTION_CACHE_ALIGNMENT;
    245246#else
    246247  return 0;
     
    254255 */
    255256void
    256 rtems_freeze_inst_cache( void )
    257 {
    258 #if defined(_CPU_INST_CACHE_ALIGNMENT)
    259   _CPU_freeze_inst_cache();
     257rtems_cache_freeze_instruction( void )
     258{
     259#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
     260  _CPU_cache_freeze_instruction();
    260261#endif
    261262}
     
    265266 * This function unfreezes the instruction cache.
    266267 */
    267 void rtems_unfreeze_inst_cache( void )
    268 {
    269 #if defined(_CPU_INST_CACHE_ALIGNMENT)
    270   _CPU_unfreeze_inst_cache();
     268void rtems_cache_unfreeze_instruction( void )
     269{
     270#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
     271  _CPU_cache_unfreeze_instruction();
    271272#endif
    272273}
     
    275276/* Turn on the instruction cache. */
    276277void
    277 rtems_enable_inst_cache( void )
    278 {
    279 #if defined(_CPU_INST_CACHE_ALIGNMENT)
    280   _CPU_enable_inst_cache();
     278rtems_cache_enable_instruction( void )
     279{
     280#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
     281  _CPU_cache_enable_instruction();
    281282#endif
    282283}
     
    285286/* Turn off the instruction cache. */
    286287void
    287 rtems_disable_inst_cache( void )
    288 {
    289 #if defined(_CPU_INST_CACHE_ALIGNMENT)
    290   _CPU_disable_inst_cache();
    291 #endif
    292 }
     288rtems_cache_disable_instruction( void )
     289{
     290#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
     291  _CPU_cache_disable_instruction();
     292#endif
     293}
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