Changeset 5e77d129 in rtems for c/src/lib/libcpu/powerpc


Ignore:
Timestamp:
Jun 14, 2000, 8:32:44 PM (20 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
b91b1cf
Parents:
9b05600
Message:

Patch from John Cotton <john.cotton@…> to correct cache
routine naming to follow RTEMS package/object.method rule.
This patch also eliminated calls to the obsolete routine
m68k_enable_caching.

Location:
c/src/lib/libcpu/powerpc
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c

    r9b05600 r5e77d129  
    400400    /* Check that the buffer is ours */
    401401    if ((RxBd[SCC2_MINOR]->status & M8xx_BD_EMPTY) == 0) {
    402       rtems_invalidate_multiple_data_cache_lines(
     402      rtems_cache_invalidate_multiple_data_lines(
    403403        (const void *) RxBd[SCC2_MINOR]->buffer,
    404404        RxBd[SCC2_MINOR]->length );
     
    443443    /* Check that the buffer is ours */
    444444    if ((RxBd[SCC3_MINOR]->status & M8xx_BD_EMPTY) == 0) {
    445       rtems_invalidate_multiple_data_cache_lines(
     445      rtems_cache_invalidate_multiple_data_lines(
    446446        (const void *) RxBd[SCC3_MINOR]->buffer,
    447447        RxBd[SCC3_MINOR]->length );
     
    485485    /* Check that the buffer is ours */
    486486    if ((RxBd[SCC4_MINOR]->status & M8xx_BD_EMPTY) == 0) {
    487       rtems_invalidate_multiple_data_cache_lines(
     487      rtems_cache_invalidate_multiple_data_lines(
    488488        (const void *) RxBd[SCC4_MINOR]->buffer,
    489489        RxBd[SCC4_MINOR]->length );
     
    527527    /* Check that the buffer is ours */
    528528    if ((RxBd[SMC1_MINOR]->status & M8xx_BD_EMPTY) == 0) {
    529       rtems_invalidate_multiple_data_cache_lines(
     529      rtems_cache_invalidate_multiple_data_lines(
    530530        (const void *) RxBd[SMC1_MINOR]->buffer,
    531531        RxBd[SMC1_MINOR]->length );
     
    569569    /* Check that the buffer is ours */
    570570    if ((RxBd[SMC2_MINOR]->status & M8xx_BD_EMPTY) == 0) {
    571       rtems_invalidate_multiple_data_cache_lines(
     571      rtems_cache_invalidate_multiple_data_lines(
    572572        (const void *) RxBd[SMC2_MINOR]->buffer,
    573573        RxBd[SMC2_MINOR]->length );
     
    985985    return -1;
    986986  }
    987   rtems_invalidate_multiple_data_cache_lines(
     987  rtems_cache_invalidate_multiple_data_lines(
    988988    (const void *) RxBd[minor]->buffer,
    989989    RxBd[minor]->length
     
    10051005)
    10061006{
    1007   rtems_flush_multiple_data_cache_lines( buf, len );
     1007  rtems_cache_flush_multiple_data_lines( buf, len );
    10081008  TxBd[minor]->buffer = (char *) buf;
    10091009  TxBd[minor]->length = len;
     
    10241024      continue;
    10251025    txBuf[minor] = *buf++;
    1026     rtems_flush_multiple_data_cache_lines(
     1026    rtems_cache_flush_multiple_data_lines(
    10271027       (const void *) TxBd[minor]->buffer,
    10281028       TxBd[minor]->length
  • c/src/lib/libcpu/powerpc/shared/src/cache.c

    r9b05600 r5e77d129  
    4343  } while (0)
    4444
    45 void _CPU_enable_data_cache (
     45void _CPU_cache_enable_data (
    4646        void )
    4747{
     
    5252}
    5353
    54 void _CPU_disable_data_cache (
     54void _CPU_cache_disable_data (
    5555        void )
    5656{
     
    6161}
    6262
    63 void _CPU_enable_inst_cache (
     63void _CPU_cache_enable_inst (
    6464        void )
    6565{
     
    7070}
    7171
    72 void _CPU_disable_inst_cache (
     72void _CPU_cache_disable_inst (
    7373        void )
    7474{
     
    8686  __asm__ volatile ("isync\n"::)
    8787
    88 void _CPU_flush_1_data_cache_line(
     88void _CPU_cache_flush_1_data_line(
    8989        const void * _address )
    9090{
     
    9393}
    9494
    95 void _CPU_invalidate_1_data_cache_line(
     95void _CPU_cache_invalidate_1_data_line(
    9696        const void * _address )
    9797{
     
    100100}
    101101
    102 void _CPU_flush_entire_data_cache ( void ) {}
    103 void _CPU_invalidate_entire_data_cache ( void ) {}
    104 void _CPU_freeze_data_cache ( void ) {}
    105 void _CPU_unfreeze_data_cache ( void ) {}
     102void _CPU_cache_flush_entire_data ( void ) {}
     103void _CPU_cache_invalidate_entire_data ( void ) {}
     104void _CPU_cache_freeze_data ( void ) {}
     105void _CPU_cache_unfreeze_data ( void ) {}
    106106
    107 void _CPU_enable_data_cache ( void )
     107void _CPU_cache_enable_data ( void )
    108108{
    109109  unsigned32 r1;
     
    113113}
    114114
    115 void _CPU_disable_data_cache ( void )
     115void _CPU_cache_disable_data ( void )
    116116{
    117117  unsigned32 r1;
     
    121121}
    122122
    123 void _CPU_invalidate_1_inst_cache_line(
     123void _CPU_cache_invalidate_1_inst_line(
    124124        const void * _address )
    125125{
     
    128128}
    129129
    130 void _CPU_invalidate_entire_inst_cache ( void ) {}
    131 void _CPU_freeze_inst_cache ( void ) {}
    132 void _CPU_unfreeze_inst_cache ( void ) {}
     130void _CPU_cache_invalidate_entire_inst ( void ) {}
     131void _CPU_cache_freeze_inst ( void ) {}
     132void _CPU_cache_unfreeze_inst ( void ) {}
    133133
    134 void _CPU_enable_inst_cache ( void )
     134void _CPU_cache_enable_inst ( void )
    135135{
    136136  unsigned32 r1;
     
    140140}
    141141
    142 void _CPU_disable_inst_cache ( void )
     142void _CPU_cache_disable_inst ( void )
    143143{
    144144  unsigned32 r1;
  • c/src/lib/libcpu/powerpc/shared/src/cache_.h

    r9b05600 r5e77d129  
    1616
    1717#if defined(ppc603)                     /* And possibly others */
    18 #define _CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
    19 #define _CPU_INST_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
     18#define CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
     19#define CPU_INSTRUCTION_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
    2020
    2121#elif ( defined(mpc860) || defined(mpc821) )
    2222
    23 #define _CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
    24 #define _CPU_INST_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
     23#define CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
     24#define CPU_INSTRUCTION_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
    2525
    2626#endif
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