Changeset 5e77d129 in rtems for c/src/lib/libcpu/i386/cache.c


Ignore:
Timestamp:
Jun 14, 2000, 8:32:44 PM (21 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
b91b1cf
Parents:
9b05600
Message:

Patch from John Cotton <john.cotton@…> to correct cache
routine naming to follow RTEMS package/object.method rule.
This patch also eliminated calls to the obsolete routine
m68k_enable_caching.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/i386/cache.c

    r9b05600 r5e77d129  
    1616  regCr0.cr0.no_write_through = 1;
    1717  i386_set_cr0( regCr0.i );
    18   rtems_flush_entire_data_cache();
     18  rtems_cache_flush_entire_data();
    1919}
    2020
     
    3030  regCr0.cr0.no_write_through = 0;
    3131  i386_set_cr0( regCr0.i );
    32   /*rtems_flush_entire_data_cache();*/
     32  /*rtems_cache_flush_entire_data();*/
    3333}
    3434
     
    3939 * it does nothing by default.
    4040 *
    41  * FIXME: Definitions for I386_CACHE_ALIGNMENT are missing above for
    42  *        each CPU. The routines below should be implemented per CPU,
     41 * FIXME: The routines below should be implemented per CPU,
    4342 *        to accomodate the capabilities of each.
    4443 */
    4544
    46 /* FIXME: I don't belong here. */
    47 #define I386_CACHE_ALIGNMENT 16
     45#if defined(I386_CACHE_ALIGNMENT)
     46void _CPU_cache_flush_1_data_line(const void *d_addr) {}
     47void _CPU_cache_invalidate_1_data_line(const void *d_addr) {}
     48void _CPU_cache_freeze_data(void) {}
     49void _CPU_cache_unfreeze_data(void) {}
     50void _CPU_cache_invalidate_1_instruction_line ( const void *d_addr ) {}
     51void _CPU_cache_freeze_instruction(void) {}
     52void _CPU_cache_unfreeze_instruction(void) {}
    4853
    49 #if defined(I386_CACHE_ALIGNMENT)
    50 #define _CPU_DATA_CACHE_ALIGNMENT I386_CACHE_ALIGNMENT
    51 #define _CPU_INST_CACHE_ALIGNEMNT I386_CACHE_ALIGNMENT
    52 
    53 void _CPU_flush_1_data_cache_line(const void *d_addr) {}
    54 void _CPU_invalidate_1_data_cache_line(const void *d_addr) {}
    55 void _CPU_freeze_data_cache(void) {}
    56 void _CPU_unfreeze_data_cache(void) {}
    57 void _CPU_invalidate_1_inst_cache_line ( const void *d_addr ) {}
    58 void _CPU_freeze_inst_cache(void) {}
    59 void _CPU_unfreeze_inst_cache(void) {}
    60 
    61 void _CPU_flush_entire_data_cache(void)
     54void _CPU_cache_flush_entire_data(void)
    6255{
    6356  asm volatile ("wbinvd");
    6457}
    65 void _CPU_invalidate_entire_data_cache(void)
     58void _CPU_cache_invalidate_entire_data(void)
    6659{
    6760  asm volatile ("invd");
    6861}
    6962
    70 void _CPU_enable_data_cache(void)
     63void _CPU_cache_enable_data(void)
    7164{
    7265        _CPU_enable_cache();
    7366}
    7467
    75 void _CPU_disable_data_cache(void)
     68void _CPU_cache_disable_data(void)
    7669{
    7770        _CPU_disable_cache();
    7871}
    7972
    80 void _CPU_invalidate_entire_inst_cache(void)
     73void _CPU_cache_invalidate_entire_instruction(void)
    8174{
    8275  asm volatile ("invd");
    8376}
    8477
    85 void _CPU_enable_inst_cache(void)
     78void _CPU_cache_enable_instruction(void)
    8679{
    8780  _CPU_enable_cache();
    8881}
    8982
    90 void _CPU_disable_inst_cache( void )
     83void _CPU_cache_disable_instruction( void )
    9184{
    9285  _CPU_disable_cache();
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