Changeset 5e77d129 in rtems


Ignore:
Timestamp:
Jun 14, 2000, 8:32:44 PM (20 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
b91b1cf
Parents:
9b05600
Message:

Patch from John Cotton <john.cotton@…> to correct cache
routine naming to follow RTEMS package/object.method rule.
This patch also eliminated calls to the obsolete routine
m68k_enable_caching.

Location:
c/src/lib
Files:
18 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/m68k/dmv152/startup/bspstart.c

    r9b05600 r5e77d129  
    8585   */
    8686
    87   m68k_enable_caching();
     87  rtems_cache_enable_instruction();
    8888
    8989  /*
  • c/src/lib/libbsp/m68k/idp/startup/bspstart.c

    r9b05600 r5e77d129  
    9191  m68k_set_vbr( &M68Kvec );
    9292
    93   m68k_enable_caching();
     93  rtems_cache_enable_instruction();
    9494
    9595  /*
  • c/src/lib/libbsp/m68k/mvme136/startup/bspstart.c

    r9b05600 r5e77d129  
    7474  (*(rtems_unsigned8 *)0xfffb0067) = 0x7f; /* make VME access round-robin */
    7575
    76   m68k_enable_caching();
     76  rtems_cache_enable_instruction();
    7777
    7878  /*
  • c/src/lib/libbsp/m68k/mvme147/startup/bspstart.c

    r9b05600 r5e77d129  
    8080      /* make VME access round-robin */
    8181
    82   m68k_enable_caching();
     82  rtems_cache_enable_instruction();
    8383
    8484  /*
  • c/src/lib/libbsp/m68k/mvme147s/startup/bspstart.c

    r9b05600 r5e77d129  
    140140  /* Disable D32 transfers : they don't work on my VMEbus rack */
    141141
    142   m68k_enable_caching();
     142  rtems_cache_enable_instruction();
    143143
    144144  /*
  • c/src/lib/libbsp/powerpc/mbx8xx/network/network.c

    r9b05600 r5e77d129  
    747747                         * Invalidate the buffer for this descriptor
    748748                         */
    749                         rtems_invalidate_multiple_data_cache_lines(rxBd->buffer, rxBd->length);
     749                        rtems_cache_invalidate_multiple_data_lines(rxBd->buffer, rxBd->length);
    750750     
    751751      m = sc->rxMbuf[rxBdIndex];
     
    883883                         * Invalidate the buffer for this descriptor
    884884                         */
    885                         rtems_invalidate_multiple_data_cache_lines(rxBd->buffer, rxBd->length);
     885                        rtems_cache_invalidate_multiple_data_lines(rxBd->buffer, rxBd->length);
    886886     
    887887      m = sc->rxMbuf[rxBdIndex];
     
    10231023       * Flush the buffer for this descriptor
    10241024       */
    1025       rtems_flush_multiple_data_cache_lines(txBd->buffer, txBd->length);
     1025      rtems_cache_flush_multiple_data_lines(txBd->buffer, txBd->length);
    10261026     
    10271027      sc->txMbuf[sc->txBdHead] = m;
     
    11511151       * Flush the buffer for this descriptor
    11521152       */
    1153       rtems_flush_multiple_data_cache_lines(txBd->buffer, txBd->length);
     1153      rtems_cache_flush_multiple_data_lines(txBd->buffer, txBd->length);
    11541154     
    11551155      sc->txMbuf[sc->txBdHead] = m;
  • c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c

    r9b05600 r5e77d129  
    137137   */
    138138  #ifdef INSTRUCTION_CACHE_ENABLE
    139         rtems_enable_inst_cache();
     139        rtems_cache_enable_instruction();
    140140  #endif
    141141
    142142  #ifdef DATA_CACHE_ENABLE
    143         rtems_enable_data_cache();
     143        rtems_cache_enable_data();
    144144  #endif
    145145   
  • c/src/lib/libcpu/i386/cache.c

    r9b05600 r5e77d129  
    1616  regCr0.cr0.no_write_through = 1;
    1717  i386_set_cr0( regCr0.i );
    18   rtems_flush_entire_data_cache();
     18  rtems_cache_flush_entire_data();
    1919}
    2020
     
    3030  regCr0.cr0.no_write_through = 0;
    3131  i386_set_cr0( regCr0.i );
    32   /*rtems_flush_entire_data_cache();*/
     32  /*rtems_cache_flush_entire_data();*/
    3333}
    3434
     
    3939 * it does nothing by default.
    4040 *
    41  * FIXME: Definitions for I386_CACHE_ALIGNMENT are missing above for
    42  *        each CPU. The routines below should be implemented per CPU,
     41 * FIXME: The routines below should be implemented per CPU,
    4342 *        to accomodate the capabilities of each.
    4443 */
    4544
    46 /* FIXME: I don't belong here. */
    47 #define I386_CACHE_ALIGNMENT 16
     45#if defined(I386_CACHE_ALIGNMENT)
     46void _CPU_cache_flush_1_data_line(const void *d_addr) {}
     47void _CPU_cache_invalidate_1_data_line(const void *d_addr) {}
     48void _CPU_cache_freeze_data(void) {}
     49void _CPU_cache_unfreeze_data(void) {}
     50void _CPU_cache_invalidate_1_instruction_line ( const void *d_addr ) {}
     51void _CPU_cache_freeze_instruction(void) {}
     52void _CPU_cache_unfreeze_instruction(void) {}
    4853
    49 #if defined(I386_CACHE_ALIGNMENT)
    50 #define _CPU_DATA_CACHE_ALIGNMENT I386_CACHE_ALIGNMENT
    51 #define _CPU_INST_CACHE_ALIGNEMNT I386_CACHE_ALIGNMENT
    52 
    53 void _CPU_flush_1_data_cache_line(const void *d_addr) {}
    54 void _CPU_invalidate_1_data_cache_line(const void *d_addr) {}
    55 void _CPU_freeze_data_cache(void) {}
    56 void _CPU_unfreeze_data_cache(void) {}
    57 void _CPU_invalidate_1_inst_cache_line ( const void *d_addr ) {}
    58 void _CPU_freeze_inst_cache(void) {}
    59 void _CPU_unfreeze_inst_cache(void) {}
    60 
    61 void _CPU_flush_entire_data_cache(void)
     54void _CPU_cache_flush_entire_data(void)
    6255{
    6356  asm volatile ("wbinvd");
    6457}
    65 void _CPU_invalidate_entire_data_cache(void)
     58void _CPU_cache_invalidate_entire_data(void)
    6659{
    6760  asm volatile ("invd");
    6861}
    6962
    70 void _CPU_enable_data_cache(void)
     63void _CPU_cache_enable_data(void)
    7164{
    7265        _CPU_enable_cache();
    7366}
    7467
    75 void _CPU_disable_data_cache(void)
     68void _CPU_cache_disable_data(void)
    7669{
    7770        _CPU_disable_cache();
    7871}
    7972
    80 void _CPU_invalidate_entire_inst_cache(void)
     73void _CPU_cache_invalidate_entire_instruction(void)
    8174{
    8275  asm volatile ("invd");
    8376}
    8477
    85 void _CPU_enable_inst_cache(void)
     78void _CPU_cache_enable_instruction(void)
    8679{
    8780  _CPU_enable_cache();
    8881}
    8982
    90 void _CPU_disable_inst_cache( void )
     83void _CPU_cache_disable_instruction( void )
    9184{
    9285  _CPU_disable_cache();
  • c/src/lib/libcpu/i386/cache_.h

    r9b05600 r5e77d129  
    77
    88#define I386_CACHE_ALIGNMENT 16
    9 #define _CPU_DATA_CACHE_ALIGNMENT I386_CACHE_ALIGNMENT
    10 #define _CPU_INST_CACHE_ALIGNEMNT I386_CACHE_ALIGNMENT
     9#define CPU_DATA_CACHE_ALIGNMENT I386_CACHE_ALIGNMENT
     10#define CPU_INSTRUCTION_CACHE_ALIGNEMNT I386_CACHE_ALIGNMENT
    1111
    1212#include <libcpu/cache.h>
  • c/src/lib/libcpu/i386/page.c

    r9b05600 r5e77d129  
    4646  cr0 regCr0;
    4747
    48   rtems_flush_entire_data_cache();
     48  rtems_cache_flush_entire_data();
    4949  regCr0.i = i386_get_cr0();
    5050  regCr0.cr0.paging = 0;
     
    6161  regCr0.cr0.paging = 1;
    6262  i386_set_cr0( regCr0.i );
    63   rtems_flush_entire_data_cache();
     63  rtems_cache_flush_entire_data();
    6464}
    6565
  • c/src/lib/libcpu/m68k/shared/cache/cache.c

    r9b05600 r5e77d129  
    5353/* Only the mc68030 has a data cache; it is writethrough only. */
    5454
    55 void _CPU_flush_1_data_cache_line ( const void * d_addr ) {}
    56 void _CPU_flush_entire_data_cache ( const void * d_addr ) {}
     55void _CPU_cache_flush_1_data_line ( const void * d_addr ) {}
     56void _CPU_cache_flush_entire_data ( const void * d_addr ) {}
    5757
    58 void _CPU_invalidate_1_data_cache_line (
     58void _CPU_cache_invalidate_1_data_line (
    5959  const void * d_addr )
    6060{
     
    6464}
    6565
    66 void _CPU_invalidate_entire_data_cache ( void )
     66void _CPU_cache_invalidate_entire_data ( void )
    6767{
    6868  _CPU_CACR_OR( 0x00000800 );
    6969}
    7070
    71 void _CPU_freeze_data_cache ( void )
     71void _CPU_cache_freeze_data ( void )
    7272{
    7373  _CPU_CACR_OR( 0x00000200 );
    7474}
    7575
    76 void _CPU_unfreeze_data_cache ( void )
     76void _CPU_cache_unfreeze_data ( void )
    7777{
    7878  _CPU_CACR_AND( 0xFFFFFDFF );
    7979}
    8080
    81 void _CPU_enable_data_cache ( void )
     81void _CPU_cache_enable_data ( void )
    8282{
    8383  _CPU_CACR_OR( 0x00000100 );
    8484}
    85 void _CPU_disable_data_cache (  void )
     85void _CPU_cache_disable_data (  void )
    8686{
    8787  _CPU_CACR_AND( 0xFFFFFEFF );
     
    9292/* Both the 68020 and 68030 have instruction caches */
    9393
    94 void _CPU_invalidate_1_inst_cache_line (
     94void _CPU_cache_invalidate_1_instruction_line (
    9595  const void * d_addr )
    9696{
     
    100100}
    101101
    102 void _CPU_invalidate_entire_inst_cache ( void )
     102void _CPU_cache_invalidate_entire_instruction ( void )
    103103{
    104104  _CPU_CACR_OR( 0x00000008 );
    105105}
    106106
    107 void _CPU_freeze_inst_cache ( void )
     107void _CPU_cache_freeze_instruction ( void )
    108108{
    109109  _CPU_CACR_OR( 0x00000002);
    110110}
    111111
    112 void _CPU_unfreeze_inst_cache ( void )
     112void _CPU_cache_unfreeze_instruction ( void )
    113113{
    114114  _CPU_CACR_AND( 0xFFFFFFFD );
    115115}
    116116
    117 void _CPU_enable_inst_cache ( void )
     117void _CPU_cache_enable_instruction ( void )
    118118{
    119119  _CPU_CACR_OR( 0x00000001 );
    120120}
    121121
    122 void _CPU_disable_inst_cache (  void )
     122void _CPU_cache_disable_instruction (   void )
    123123{
    124124  _CPU_CACR_AND( 0xFFFFFFFE );
     
    129129
    130130/* Cannot be frozen */
    131 void _CPU_freeze_data_cache ( void ) {}
    132 void _CPU_unfreeze_data_cache ( void ) {}
    133 void _CPU_freeze_inst_cache ( void ) {}
    134 void _CPU_unfreeze_inst_cache ( void ) {}
     131void _CPU_cache_freeze_data ( void ) {}
     132void _CPU_cache_unfreeze_data ( void ) {}
     133void _CPU_cache_freeze_instruction ( void ) {}
     134void _CPU_cache_unfreeze_instruction ( void ) {}
    135135
    136 void _CPU_flush_1_data_cache_line (
     136void _CPU_cache_flush_1_data_line (
    137137  const void * d_addr )
    138138{
     
    141141}
    142142
    143 void _CPU_invalidate_1_data_cache_line (
     143void _CPU_cache_invalidate_1_data_line (
    144144  const void * d_addr )
    145145{
     
    148148}
    149149
    150 void _CPU_flush_entire_data_cache ( void )
     150void _CPU_cache_flush_entire_data ( void )
    151151{
    152152        asm volatile ( "cpusha %%dc" :: );
    153153}
    154154
    155 void _CPU_invalidate_entire_data_cache ( void )
     155void _CPU_cache_invalidate_entire_data ( void )
    156156{
    157157        asm volatile ( "cinva %%dc" :: );
    158158}
    159159
    160 void _CPU_enable_data_cache ( void )
     160void _CPU_cache_enable_data ( void )
    161161{
    162162  _CPU_CACR_OR( 0x80000000 );
    163163}
    164164
    165 void _CPU_disable_data_cache ( void )
     165void _CPU_cache_disable_data ( void )
    166166{
    167167  _CPU_CACR_AND( 0x7FFFFFFF );
    168168}
    169169
    170 void _CPU_invalidate_1_inst_cache_line (
     170void _CPU_cache_invalidate_1_instruction_line (
    171171  const void * i_addr )
    172172{
     
    175175}
    176176
    177 void _CPU_invalidate_entire_inst_cache ( void )
     177void _CPU_cache_invalidate_entire_instruction ( void )
    178178{
    179179                asm volatile ( "cinva %%ic" :: );
    180180}
    181181
    182 void _CPU_enable_inst_cache ( void )
     182void _CPU_cache_enable_instruction ( void )
    183183{
    184184  _CPU_CACR_OR( 0x00008000 );
    185185}
    186186
    187 void _CPU_disable_inst_cache ( void )
     187void _CPU_cache_disable_instruction ( void )
    188188{
    189189        _CPU_CACR_AND( 0xFFFF7FFF );
  • c/src/lib/libcpu/m68k/shared/cache/cache_.h

    r9b05600 r5e77d129  
    77
    88#if defined(__mc68020__)
    9 #define M68K_INST_CACHE_ALIGNMENT 16
     9#define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
    1010#elif defined(__mc68030__)
    11 #define M68K_INST_CACHE_ALIGNMENT 16
     11#define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
    1212#define M68K_DATA_CACHE_ALIGNMENT 16
    1313#elif ( defined(__mc68040__) || defined (__mc68060__) )
    14 #define M68K_INST_CACHE_ALIGNMENT 16
     14#define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
    1515#define M68K_DATA_CACHE_ALIGNMENT 16
    1616#endif
    1717
    1818#if defined(M68K_DATA_CACHE_ALIGNMENT)
    19 #define _CPU_DATA_CACHE_ALIGNMENT M68K_DATA_CACHE_ALIGNMENT
     19#define CPU_DATA_CACHE_ALIGNMENT M68K_DATA_CACHE_ALIGNMENT
    2020#endif
    2121
    22 #if defined(M68K_INST_CACHE_ALIGNMENT)
    23 #define _CPU_INST_CACHE_ALIGNMENT M68K_INST_CACHE_ALIGNMENT
     22#if defined(M68K_INSTRUCTION_CACHE_ALIGNMENT)
     23#define CPU_INSTRUCTION_CACHE_ALIGNMENT M68K_INSTRUCTION_CACHE_ALIGNMENT
    2424#endif
    2525
  • c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c

    r9b05600 r5e77d129  
    400400    /* Check that the buffer is ours */
    401401    if ((RxBd[SCC2_MINOR]->status & M8xx_BD_EMPTY) == 0) {
    402       rtems_invalidate_multiple_data_cache_lines(
     402      rtems_cache_invalidate_multiple_data_lines(
    403403        (const void *) RxBd[SCC2_MINOR]->buffer,
    404404        RxBd[SCC2_MINOR]->length );
     
    443443    /* Check that the buffer is ours */
    444444    if ((RxBd[SCC3_MINOR]->status & M8xx_BD_EMPTY) == 0) {
    445       rtems_invalidate_multiple_data_cache_lines(
     445      rtems_cache_invalidate_multiple_data_lines(
    446446        (const void *) RxBd[SCC3_MINOR]->buffer,
    447447        RxBd[SCC3_MINOR]->length );
     
    485485    /* Check that the buffer is ours */
    486486    if ((RxBd[SCC4_MINOR]->status & M8xx_BD_EMPTY) == 0) {
    487       rtems_invalidate_multiple_data_cache_lines(
     487      rtems_cache_invalidate_multiple_data_lines(
    488488        (const void *) RxBd[SCC4_MINOR]->buffer,
    489489        RxBd[SCC4_MINOR]->length );
     
    527527    /* Check that the buffer is ours */
    528528    if ((RxBd[SMC1_MINOR]->status & M8xx_BD_EMPTY) == 0) {
    529       rtems_invalidate_multiple_data_cache_lines(
     529      rtems_cache_invalidate_multiple_data_lines(
    530530        (const void *) RxBd[SMC1_MINOR]->buffer,
    531531        RxBd[SMC1_MINOR]->length );
     
    569569    /* Check that the buffer is ours */
    570570    if ((RxBd[SMC2_MINOR]->status & M8xx_BD_EMPTY) == 0) {
    571       rtems_invalidate_multiple_data_cache_lines(
     571      rtems_cache_invalidate_multiple_data_lines(
    572572        (const void *) RxBd[SMC2_MINOR]->buffer,
    573573        RxBd[SMC2_MINOR]->length );
     
    985985    return -1;
    986986  }
    987   rtems_invalidate_multiple_data_cache_lines(
     987  rtems_cache_invalidate_multiple_data_lines(
    988988    (const void *) RxBd[minor]->buffer,
    989989    RxBd[minor]->length
     
    10051005)
    10061006{
    1007   rtems_flush_multiple_data_cache_lines( buf, len );
     1007  rtems_cache_flush_multiple_data_lines( buf, len );
    10081008  TxBd[minor]->buffer = (char *) buf;
    10091009  TxBd[minor]->length = len;
     
    10241024      continue;
    10251025    txBuf[minor] = *buf++;
    1026     rtems_flush_multiple_data_cache_lines(
     1026    rtems_cache_flush_multiple_data_lines(
    10271027       (const void *) TxBd[minor]->buffer,
    10281028       TxBd[minor]->length
  • c/src/lib/libcpu/powerpc/shared/src/cache.c

    r9b05600 r5e77d129  
    4343  } while (0)
    4444
    45 void _CPU_enable_data_cache (
     45void _CPU_cache_enable_data (
    4646        void )
    4747{
     
    5252}
    5353
    54 void _CPU_disable_data_cache (
     54void _CPU_cache_disable_data (
    5555        void )
    5656{
     
    6161}
    6262
    63 void _CPU_enable_inst_cache (
     63void _CPU_cache_enable_inst (
    6464        void )
    6565{
     
    7070}
    7171
    72 void _CPU_disable_inst_cache (
     72void _CPU_cache_disable_inst (
    7373        void )
    7474{
     
    8686  __asm__ volatile ("isync\n"::)
    8787
    88 void _CPU_flush_1_data_cache_line(
     88void _CPU_cache_flush_1_data_line(
    8989        const void * _address )
    9090{
     
    9393}
    9494
    95 void _CPU_invalidate_1_data_cache_line(
     95void _CPU_cache_invalidate_1_data_line(
    9696        const void * _address )
    9797{
     
    100100}
    101101
    102 void _CPU_flush_entire_data_cache ( void ) {}
    103 void _CPU_invalidate_entire_data_cache ( void ) {}
    104 void _CPU_freeze_data_cache ( void ) {}
    105 void _CPU_unfreeze_data_cache ( void ) {}
     102void _CPU_cache_flush_entire_data ( void ) {}
     103void _CPU_cache_invalidate_entire_data ( void ) {}
     104void _CPU_cache_freeze_data ( void ) {}
     105void _CPU_cache_unfreeze_data ( void ) {}
    106106
    107 void _CPU_enable_data_cache ( void )
     107void _CPU_cache_enable_data ( void )
    108108{
    109109  unsigned32 r1;
     
    113113}
    114114
    115 void _CPU_disable_data_cache ( void )
     115void _CPU_cache_disable_data ( void )
    116116{
    117117  unsigned32 r1;
     
    121121}
    122122
    123 void _CPU_invalidate_1_inst_cache_line(
     123void _CPU_cache_invalidate_1_inst_line(
    124124        const void * _address )
    125125{
     
    128128}
    129129
    130 void _CPU_invalidate_entire_inst_cache ( void ) {}
    131 void _CPU_freeze_inst_cache ( void ) {}
    132 void _CPU_unfreeze_inst_cache ( void ) {}
     130void _CPU_cache_invalidate_entire_inst ( void ) {}
     131void _CPU_cache_freeze_inst ( void ) {}
     132void _CPU_cache_unfreeze_inst ( void ) {}
    133133
    134 void _CPU_enable_inst_cache ( void )
     134void _CPU_cache_enable_inst ( void )
    135135{
    136136  unsigned32 r1;
     
    140140}
    141141
    142 void _CPU_disable_inst_cache ( void )
     142void _CPU_cache_disable_inst ( void )
    143143{
    144144  unsigned32 r1;
  • c/src/lib/libcpu/powerpc/shared/src/cache_.h

    r9b05600 r5e77d129  
    1616
    1717#if defined(ppc603)                     /* And possibly others */
    18 #define _CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
    19 #define _CPU_INST_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
     18#define CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
     19#define CPU_INSTRUCTION_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
    2020
    2121#elif ( defined(mpc860) || defined(mpc821) )
    2222
    23 #define _CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
    24 #define _CPU_INST_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
     23#define CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
     24#define CPU_INSTRUCTION_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
    2525
    2626#endif
  • c/src/lib/libcpu/shared/include/cache.h

    r9b05600 r5e77d129  
    1010#include <sys/types.h>
    1111
    12 void _CPU_disable_cache();
    13 void _CPU_enable_cache();
    14 
    15 void _CPU_flush_1_data_cache_line(const void *d_addr);
    16 void _CPU_invalidate_1_data_cache_line(const void *d_addr);
    17 void _CPU_freeze_data_cache(void);
    18 void _CPU_unfreeze_data_cache(void);
    19 void _CPU_invalidate_1_inst_cache_line(const void *d_addr);
    20 void _CPU_freeze_inst_cache(void);
    21 void _CPU_unfreeze_inst_cache(void);
    22 
    23 void _CPU_flush_entire_data_cache(void);
    24 void _CPU_invalidate_entire_data_cache(void);
    25 void _CPU_enable_data_cache(void);
    26 void _CPU_disable_data_cache(void);
    27 void _CPU_invalidate_entire_inst_cache(void);
    28 void _CPU_enable_inst_cache(void);
    29 void _CPU_disable_inst_cache(void);
     12void _CPU_cache_flush_1_data_line(const void *d_addr);
     13void _CPU_cache_invalidate_1_data_line(const void *d_addr);
     14void _CPU_cache_freeze_data(void);
     15void _CPU_cache_unfreeze_data(void);
     16void _CPU_cache_invalidate_1_instruction_line(const void *d_addr);
     17void _CPU_cache_freeze_instruction(void);
     18void _CPU_cache_unfreeze_instruction(void);
     19void _CPU_cache_flush_entire_data(void);
     20void _CPU_cache_invalidate_entire_data(void);
     21void _CPU_cache_enable_data(void);
     22void _CPU_cache_disable_data(void);
     23void _CPU_cache_invalidate_entire_instruction(void);
     24void _CPU_cache_enable_instruction(void);
     25void _CPU_cache_disable_instruction(void);
    3026
    3127#endif
  • c/src/lib/libcpu/shared/src/cache_aligned_malloc.c

    r9b05600 r5e77d129  
    3333   * block beyond the header.
    3434   */
    35 #if defined(_CPU_DATA_CACHE_ALIGNMENT)
     35#if defined(CPU_DATA_CACHE_ALIGNMENT)
    3636  return (void *) ((((unsigned long)
    37      malloc( nbytes + _CPU_DATA_CACHE_ALIGNMENT - 1 ))
    38         + _CPU_DATA_CACHE_ALIGNMENT - 1 ) &(~(_CPU_DATA_CACHE_ALIGNMENT - 1)) );
     37     malloc( nbytes + CPU_DATA_CACHE_ALIGNMENT - 1 ))
     38        + CPU_DATA_CACHE_ALIGNMENT - 1 ) &(~(CPU_DATA_CACHE_ALIGNMENT - 1)) );
    3939#else
    4040  return malloc( nbytes );
  • c/src/lib/libcpu/shared/src/cache_manager.c

    r9b05600 r5e77d129  
    1212 *  The functions in this file implement the API to the RTEMS Cache Manager and
    1313 *  are divided into data cache and instruction cache functions. Data cache
    14  *  functions are only declared if a data cache is supported. Instruction
    15  *  cache functions are only declared if an instruction cache is supported.
    16  *  Support for a particular cache exists only if _CPU_x_CACHE_ALIGNMENT is
    17  *  defined, where x E {DATA, INST}. These definitions are found in the CPU
    18  *  dependent source files in the supercore, often
    19  * 
    20  *  rtems/c/src/exec/score/cpu/CPU/rtems/score/CPU.h
     14 *  functions only have bodies if a data cache is supported. Instruction
     15 *  cache functions only have bodies if an instruction cache is supported.
     16 *  Support for a particular cache exists only if CPU_x_CACHE_ALIGNMENT is
     17 *  defined, where x E {DATA, INSTRUCTION}. These definitions are found in
     18 *  the Cache Manager Wrapper header files, often
     19 * 
     20 *  rtems/c/src/lib/libcpu/CPU/cache_.h
    2121 * 
    2222 *  The functions below are implemented with CPU dependent inline routines
    23  *  also found in the above file. In the event that a CPU does not support a
    24  *  specific function, the CPU dependent routine does nothing (but does exist).
     23 *  found in the cache.c files for each CPU. In the event that a CPU does
     24 *  not support a specific function for a cache it has, the CPU dependent
     25 *  routine does nothing (but does exist).
    2526 * 
    2627 *  At this point, the Cache Manager makes no considerations, and provides no
     
    4647 */
    4748void
    48 rtems_flush_multiple_data_cache_lines( const void * d_addr, size_t n_bytes )
    49 {
    50 #if defined(_CPU_DATA_CACHE_ALIGNMENT)
     49rtems_cache_flush_multiple_data_lines( const void * d_addr, size_t n_bytes )
     50{
     51#if defined(CPU_DATA_CACHE_ALIGNMENT)
    5152  const void * final_address;
    5253
     
    5859
    5960  final_address = (void *)((size_t)d_addr + n_bytes - 1);
    60   d_addr = (void *)((size_t)d_addr & ~(_CPU_DATA_CACHE_ALIGNMENT - 1));
     61  d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1));
    6162  while( d_addr <= final_address )  {
    62     _CPU_flush_1_data_cache_line( d_addr );
    63     d_addr = (void *)((size_t)d_addr + _CPU_DATA_CACHE_ALIGNMENT);
     63    _CPU_cache_flush_1_data_line( d_addr );
     64    d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT);
    6465  }
    6566#endif
     
    7475
    7576void
    76 rtems_invalidate_multiple_data_cache_lines( const void * d_addr, size_t n_bytes )
    77 {
    78 #if defined(_CPU_DATA_CACHE_ALIGNMENT)
     77rtems_cache_invalidate_multiple_data_lines( const void * d_addr, size_t n_bytes )
     78{
     79#if defined(CPU_DATA_CACHE_ALIGNMENT)
    7980  const void * final_address;
    8081
     
    8687
    8788  final_address = (void *)((size_t)d_addr + n_bytes - 1);
    88   d_addr = (void *)((size_t)d_addr & ~(_CPU_DATA_CACHE_ALIGNMENT - 1));
     89  d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1));
    8990  while( final_address > d_addr ) {
    90     _CPU_invalidate_1_data_cache_line( d_addr );
    91     d_addr = (void *)((size_t)d_addr + _CPU_DATA_CACHE_ALIGNMENT);
     91    _CPU_cache_invalidate_1_data_line( d_addr );
     92    d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT);
    9293  }
    9394#endif
     
    100101 */
    101102void
    102 rtems_flush_entire_data_cache( void )
    103 {
    104 #if defined(_CPU_DATA_CACHE_ALIGNMENT)
     103rtems_cache_flush_entire_data( void )
     104{
     105#if defined(CPU_DATA_CACHE_ALIGNMENT)
    105106   /*
    106107    * Call the CPU-specific routine
    107108    */
    108    _CPU_flush_entire_data_cache();
     109   _CPU_cache_flush_entire_data();
    109110#endif
    110111}
     
    116117 */
    117118void
    118 rtems_invalidate_entire_data_cache( void )
    119 {
    120 #if defined(_CPU_DATA_CACHE_ALIGNMENT)
     119rtems_cache_invalidate_entire_data( void )
     120{
     121#if defined(CPU_DATA_CACHE_ALIGNMENT)
    121122 /*
    122123  * Call the CPU-specific routine
    123124  */
    124125
    125  _CPU_invalidate_entire_data_cache();
     126 _CPU_cache_invalidate_entire_data();
    126127#endif
    127128}
     
    132133 */
    133134int
    134 rtems_get_data_cache_line_size( void )
    135 {
    136 #if defined(_CPU_DATA_CACHE_ALIGNMENT)
    137   return _CPU_DATA_CACHE_ALIGNMENT;
     135rtems_cache_get_data_line_size( void )
     136{
     137#if defined(CPU_DATA_CACHE_ALIGNMENT)
     138  return CPU_DATA_CACHE_ALIGNMENT;
    138139#else
    139140  return 0;
     
    147148 */
    148149void
    149 rtems_freeze_data_cache( void )
    150 {
    151 #if defined(_CPU_DATA_CACHE_ALIGNMENT)
    152   _CPU_freeze_data_cache();
     150rtems_cache_freeze_data( void )
     151{
     152#if defined(CPU_DATA_CACHE_ALIGNMENT)
     153  _CPU_cache_freeze_data();
    153154#endif
    154155}
     
    158159 * This function unfreezes the instruction cache.
    159160 */
    160 void rtems_unfreeze_data_cache( void )
    161 {
    162 #if defined(_CPU_DATA_CACHE_ALIGNMENT)
    163   _CPU_unfreeze_data_cache();
     161void rtems_cache_unfreeze_data( void )
     162{
     163#if defined(CPU_DATA_CACHE_ALIGNMENT)
     164  _CPU_cache_unfreeze_data();
    164165#endif
    165166}
     
    168169/* Turn on the data cache. */
    169170void
    170 rtems_enable_data_cache( void )
    171 {
    172 #if defined(_CPU_DATA_CACHE_ALIGNMENT)
    173   _CPU_enable_data_cache();
     171rtems_cache_enable_data( void )
     172{
     173#if defined(CPU_DATA_CACHE_ALIGNMENT)
     174  _CPU_cache_enable_data();
    174175#endif
    175176}
     
    178179/* Turn off the data cache. */
    179180void
    180 rtems_disable_data_cache( void )
    181 {
    182 #if defined(_CPU_DATA_CACHE_ALIGNMENT)
    183   _CPU_disable_data_cache();
     181rtems_cache_disable_data( void )
     182{
     183#if defined(CPU_DATA_CACHE_ALIGNMENT)
     184  _CPU_cache_disable_data();
    184185#endif
    185186}
     
    197198 */
    198199void
    199 rtems_invalidate_multiple_inst_cache_lines( const void * i_addr, size_t n_bytes )
    200 {
    201 #if defined(_CPU_INST_CACHE_ALIGNMENT)
     200rtems_cache_invalidate_multiple_instruction_lines( const void * i_addr, size_t n_bytes )
     201{
     202#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
    202203  const void * final_address;
    203204
     
    209210
    210211  final_address = (void *)((size_t)i_addr + n_bytes - 1);
    211   i_addr = (void *)((size_t)i_addr & ~(_CPU_INST_CACHE_ALIGNMENT - 1));
     212  i_addr = (void *)((size_t)i_addr & ~(CPU_INSTRUCTION_CACHE_ALIGNMENT - 1));
    212213  while( final_address > i_addr ) {
    213     _CPU_invalidate_1_inst_cache_line( i_addr );
    214     i_addr = (void *)((size_t)i_addr + _CPU_INST_CACHE_ALIGNMENT);
     214    _CPU_cache_invalidate_1_instruction_line( i_addr );
     215    i_addr = (void *)((size_t)i_addr + CPU_INSTRUCTION_CACHE_ALIGNMENT);
    215216  }
    216217#endif
     
    223224 */
    224225void
    225 rtems_invalidate_entire_inst_cache( void )
    226 {
    227 #if defined(_CPU_INST_CACHE_ALIGNMENT)
     226rtems_cache_invalidate_entire_instruction( void )
     227{
     228#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
    228229 /*
    229230  * Call the CPU-specific routine
    230231  */
    231232
    232  _CPU_invalidate_entire_inst_cache();
     233 _CPU_cache_invalidate_entire_instruction();
    233234#endif
    234235}
     
    239240 */
    240241int
    241 rtems_get_inst_cache_line_size( void )
    242 {
    243 #if defined(_CPU_INST_CACHE_ALIGNMENT)
    244   return _CPU_INST_CACHE_ALIGNMENT;
     242rtems_cache_get_instruction_line_size( void )
     243{
     244#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
     245  return CPU_INSTRUCTION_CACHE_ALIGNMENT;
    245246#else
    246247  return 0;
     
    254255 */
    255256void
    256 rtems_freeze_inst_cache( void )
    257 {
    258 #if defined(_CPU_INST_CACHE_ALIGNMENT)
    259   _CPU_freeze_inst_cache();
     257rtems_cache_freeze_instruction( void )
     258{
     259#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
     260  _CPU_cache_freeze_instruction();
    260261#endif
    261262}
     
    265266 * This function unfreezes the instruction cache.
    266267 */
    267 void rtems_unfreeze_inst_cache( void )
    268 {
    269 #if defined(_CPU_INST_CACHE_ALIGNMENT)
    270   _CPU_unfreeze_inst_cache();
     268void rtems_cache_unfreeze_instruction( void )
     269{
     270#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
     271  _CPU_cache_unfreeze_instruction();
    271272#endif
    272273}
     
    275276/* Turn on the instruction cache. */
    276277void
    277 rtems_enable_inst_cache( void )
    278 {
    279 #if defined(_CPU_INST_CACHE_ALIGNMENT)
    280   _CPU_enable_inst_cache();
     278rtems_cache_enable_instruction( void )
     279{
     280#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
     281  _CPU_cache_enable_instruction();
    281282#endif
    282283}
     
    285286/* Turn off the instruction cache. */
    286287void
    287 rtems_disable_inst_cache( void )
    288 {
    289 #if defined(_CPU_INST_CACHE_ALIGNMENT)
    290   _CPU_disable_inst_cache();
    291 #endif
    292 }
     288rtems_cache_disable_instruction( void )
     289{
     290#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
     291  _CPU_cache_disable_instruction();
     292#endif
     293}
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