Changeset 5e657e2 in rtems


Ignore:
Timestamp:
Apr 9, 2010, 12:30:39 PM (10 years ago)
Author:
Thomas Doerfler <Thomas.Doerfler@…>
Branches:
4.10, 4.11, master
Children:
a0bdb9b
Parents:
bdac0eed
Message:

Documentation. Fixed mask defines.

Location:
c/src/lib/libcpu/arm
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/arm/ChangeLog

    rbdac0eed r5e657e2  
     12010-04-08      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * shared/include/arm-cp15.h: Documentation.  Fixed mask defines.
     4
    152010-03-03      Sebastian Huber <sebastian.huber@embedded-brains.de>
    26
  • c/src/lib/libcpu/arm/shared/include/arm-cp15.h

    rbdac0eed r5e657e2  
    22 * @file
    33 *
    4  * @ingroup arm
     4 * @ingroup ScoreCPUARMCP15
    55 *
    66 * @brief ARM co-processor 15 (CP15) API.
     
    88
    99/*
    10  * Copyright (c) 2009
     10 * Copyright (c) 2009, 2010
    1111 * embedded brains GmbH
    1212 * Obere Lagerstr. 30
     
    2929#endif /* __cplusplus */
    3030
     31#define ARM_CP15_CACHE_PREPARE_MVA(mva) \
     32  ((const void *) (((uint32_t) (mva)) & ~0x1fU))
     33
     34#define ARM_CP15_TLB_PREPARE_MVA(mva) \
     35  ((const void *) (((uint32_t) (mva)) & ~0x3fU))
     36
     37/**
     38 * @defgroup ScoreCPUARMCP15 ARM Co-Processor 15 Support
     39 *
     40 * @ingroup ScoreCPUARM
     41 *
     42 * @brief ARM co-processor 15 (CP15) support.
     43 *
     44 * @{
     45 */
     46
     47/**
     48 * @name MMU Defines
     49 *
     50 * @{
     51 */
     52
    3153#define ARM_MMU_SECT_BASE_SHIFT 20
    32 #define ARM_MMU_SECT_BASE_MASK 0xfffU
     54#define ARM_MMU_SECT_BASE_MASK (0xfffU << ARM_MMU_SECT_BASE_SHIFT)
    3355#define ARM_MMU_SECT_DOMAIN_SHIFT 5
    34 #define ARM_MMU_SECT_DOMAIN_MASK 0xfU
     56#define ARM_MMU_SECT_DOMAIN_MASK (0xfU << ARM_MMU_SECT_DOMAIN_SHIFT)
    3557#define ARM_MMU_SECT_AP_1 (1U << 11)
    3658#define ARM_MMU_SECT_AP_0 (1U << 10)
    3759#define ARM_MMU_SECT_AP_SHIFT 10
    38 #define ARM_MMU_SECT_AP_MASK 0x3U
     60#define ARM_MMU_SECT_AP_MASK (0x3U << ARM_MMU_SECT_AP_SHIFT)
    3961#define ARM_MMU_SECT_C (1U << 3)
    4062#define ARM_MMU_SECT_B (1U << 2)
     
    4971#define ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT 4096U
    5072
    51 static inline uint32_t arm_cp15_get_id_code(void)
    52 {
    53   ARM_SWITCH_REGISTERS;
    54   uint32_t val;
    55 
    56   asm volatile (
    57     ARM_SWITCH_TO_ARM
    58     "mrc p15, 0, %[val], c0, c0, 0\n"
    59     ARM_SWITCH_BACK
    60     : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
    61   );
    62 
    63   return val;
    64 }
    65 
    66 static inline uint32_t arm_cp15_get_cache_type(void)
    67 {
    68   ARM_SWITCH_REGISTERS;
    69   uint32_t val;
    70 
    71   asm volatile (
    72     ARM_SWITCH_TO_ARM
    73     "mrc p15, 0, %[val], c0, c0, 1\n"
    74     ARM_SWITCH_BACK
    75     : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
    76   );
    77 
    78   return val;
    79 }
    80 
    81 static inline uint32_t arm_cp15_get_tcm_status(void)
    82 {
    83   ARM_SWITCH_REGISTERS;
    84   uint32_t val;
    85 
    86   asm volatile (
    87     ARM_SWITCH_TO_ARM
    88     "mrc p15, 0, %[val], c0, c0, 2\n"
    89     ARM_SWITCH_BACK
    90     : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
    91   );
    92 
    93   return val;
    94 }
     73/** @} */
     74
     75/**
     76 * @name Control Register Defines
     77 *
     78 * @{
     79 */
    9580
    9681#define ARM_CP15_CTRL_L4 (1U << 15)
     
    10590#define ARM_CP15_CTRL_M (1U << 0)
    10691
    107 static inline uint32_t arm_cp15_get_control(void)
    108 {
    109   ARM_SWITCH_REGISTERS;
    110   uint32_t val;
    111 
    112   asm volatile (
    113     ARM_SWITCH_TO_ARM
    114     "mrc p15, 0, %[val], c1, c0, 0\n"
    115     ARM_SWITCH_BACK
    116     : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
    117   );
    118 
    119   return val;
    120 }
    121 
    122 static inline void arm_cp15_set_control(uint32_t val)
    123 {
    124   ARM_SWITCH_REGISTERS;
    125 
    126   asm volatile (
    127     ARM_SWITCH_TO_ARM
    128     "mcr p15, 0, %[val], c1, c0, 0\n"
    129     "nop\n"
    130     "nop\n"
    131     ARM_SWITCH_BACK
    132     : ARM_SWITCH_OUTPUT
    133     : [val] "r" (val)
    134     : "memory"
    135   );
    136 }
    137 
    138 static inline uint32_t *arm_cp15_get_translation_table_base(void)
    139 {
    140   ARM_SWITCH_REGISTERS;
    141   uint32_t *base;
    142 
    143   asm volatile (
    144     ARM_SWITCH_TO_ARM
    145     "mrc p15, 0, %[base], c2, c0, 0\n"
    146     ARM_SWITCH_BACK
    147     : [base] "=&r" (base) ARM_SWITCH_ADDITIONAL_OUTPUT
    148   );
    149 
    150   return base;
    151 }
    152 
    153 static inline void arm_cp15_set_translation_table_base(uint32_t *base)
    154 {
    155   ARM_SWITCH_REGISTERS;
    156 
    157   asm volatile (
    158     ARM_SWITCH_TO_ARM
    159     "mcr p15, 0, %[base], c2, c0, 0\n"
    160     ARM_SWITCH_BACK
    161     : ARM_SWITCH_OUTPUT
    162     : [base] "r" (base)
    163   );
    164 }
     92/** @} */
     93
     94/**
     95 * @name Domain Access Control Defines
     96 *
     97 * @{
     98 */
    16599
    166100#define ARM_CP15_DAC_NO_ACCESS 0x0U
     
    169103#define ARM_CP15_DAC_DOMAIN(index, val) ((val) << (2 * index))
    170104
     105/** @} */
     106
     107static inline uint32_t arm_cp15_get_id_code(void)
     108{
     109  ARM_SWITCH_REGISTERS;
     110  uint32_t val;
     111
     112  asm volatile (
     113    ARM_SWITCH_TO_ARM
     114    "mrc p15, 0, %[val], c0, c0, 0\n"
     115    ARM_SWITCH_BACK
     116    : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
     117  );
     118
     119  return val;
     120}
     121
     122static inline uint32_t arm_cp15_get_tcm_status(void)
     123{
     124  ARM_SWITCH_REGISTERS;
     125  uint32_t val;
     126
     127  asm volatile (
     128    ARM_SWITCH_TO_ARM
     129    "mrc p15, 0, %[val], c0, c0, 2\n"
     130    ARM_SWITCH_BACK
     131    : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
     132  );
     133
     134  return val;
     135}
     136
     137static inline uint32_t arm_cp15_get_control(void)
     138{
     139  ARM_SWITCH_REGISTERS;
     140  uint32_t val;
     141
     142  asm volatile (
     143    ARM_SWITCH_TO_ARM
     144    "mrc p15, 0, %[val], c1, c0, 0\n"
     145    ARM_SWITCH_BACK
     146    : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
     147  );
     148
     149  return val;
     150}
     151
     152static inline void arm_cp15_set_control(uint32_t val)
     153{
     154  ARM_SWITCH_REGISTERS;
     155
     156  asm volatile (
     157    ARM_SWITCH_TO_ARM
     158    "mcr p15, 0, %[val], c1, c0, 0\n"
     159    "nop\n"
     160    "nop\n"
     161    ARM_SWITCH_BACK
     162    : ARM_SWITCH_OUTPUT
     163    : [val] "r" (val)
     164    : "memory"
     165  );
     166}
     167
     168/**
     169 * @name MMU Functions
     170 *
     171 * @{
     172 */
     173
     174static inline uint32_t *arm_cp15_get_translation_table_base(void)
     175{
     176  ARM_SWITCH_REGISTERS;
     177  uint32_t *base;
     178
     179  asm volatile (
     180    ARM_SWITCH_TO_ARM
     181    "mrc p15, 0, %[base], c2, c0, 0\n"
     182    ARM_SWITCH_BACK
     183    : [base] "=&r" (base) ARM_SWITCH_ADDITIONAL_OUTPUT
     184  );
     185
     186  return base;
     187}
     188
     189static inline void arm_cp15_set_translation_table_base(uint32_t *base)
     190{
     191  ARM_SWITCH_REGISTERS;
     192
     193  asm volatile (
     194    ARM_SWITCH_TO_ARM
     195    "mcr p15, 0, %[base], c2, c0, 0\n"
     196    ARM_SWITCH_BACK
     197    : ARM_SWITCH_OUTPUT
     198    : [base] "r" (base)
     199  );
     200}
     201
    171202static inline uint32_t arm_cp15_get_domain_access_control(void)
    172203{
     
    280311  );
    281312}
    282 
    283 #define ARM_CP15_CACHE_PREPARE_MVA(mva) \
    284   ((const void *) (((uint32_t) (mva)) & ~0x1fU))
    285 
    286 static inline void arm_cp15_cache_invalidate(void)
    287 {
    288   ARM_SWITCH_REGISTERS;
    289   uint32_t sbz = 0;
    290 
    291   asm volatile (
    292     ARM_SWITCH_TO_ARM
    293     "mcr p15, 0, %[sbz], c7, c7, 0\n"
    294     ARM_SWITCH_BACK
    295     : ARM_SWITCH_OUTPUT
    296     : [sbz] "r" (sbz)
    297     : "memory"
    298   );
    299 }
    300 
    301 static inline void arm_cp15_instruction_cache_invalidate(void)
    302 {
    303   ARM_SWITCH_REGISTERS;
    304   uint32_t sbz = 0;
    305 
    306   asm volatile (
    307     ARM_SWITCH_TO_ARM
    308     "mcr p15, 0, %[sbz], c7, c5, 0\n"
    309     ARM_SWITCH_BACK
    310     : ARM_SWITCH_OUTPUT
    311     : [sbz] "r" (sbz)
    312     : "memory"
    313   );
    314 }
    315 
    316 static inline void arm_cp15_instruction_cache_invalidate_line(const void *mva)
    317 {
    318   ARM_SWITCH_REGISTERS;
    319 
    320   mva = ARM_CP15_CACHE_PREPARE_MVA(mva);
    321 
    322   asm volatile (
    323     ARM_SWITCH_TO_ARM
    324     "mcr p15, 0, %[mva], c7, c5, 1\n"
    325     ARM_SWITCH_BACK
    326     : ARM_SWITCH_OUTPUT
    327     : [mva] "r" (mva)
    328     : "memory"
    329   );
    330 }
    331 
    332 static inline void arm_cp15_instruction_cache_invalidate_line_by_set_and_way(uint32_t set_and_way)
    333 {
    334   ARM_SWITCH_REGISTERS;
    335 
    336   asm volatile (
    337     ARM_SWITCH_TO_ARM
    338     "mcr p15, 0, %[set_and_way], c7, c5, 2\n"
    339     ARM_SWITCH_BACK
    340     : ARM_SWITCH_OUTPUT
    341     : [set_and_way] "r" (set_and_way)
    342     : "memory"
    343   );
    344 }
    345 
    346 static inline void arm_cp15_instruction_cache_prefetch_line(const void *mva)
    347 {
    348   ARM_SWITCH_REGISTERS;
    349 
    350   mva = ARM_CP15_CACHE_PREPARE_MVA(mva);
    351 
    352   asm volatile (
    353     ARM_SWITCH_TO_ARM
    354     "mcr p15, 0, %[mva], c7, c13, 1\n"
    355     ARM_SWITCH_BACK
    356     : ARM_SWITCH_OUTPUT
    357     : [mva] "r" (mva)
    358   );
    359 }
    360 
    361 static inline void arm_cp15_data_cache_invalidate(void)
    362 {
    363   ARM_SWITCH_REGISTERS;
    364   uint32_t sbz = 0;
    365 
    366   asm volatile (
    367     ARM_SWITCH_TO_ARM
    368     "mcr p15, 0, %[sbz], c7, c6, 0\n"
    369     ARM_SWITCH_BACK
    370     : ARM_SWITCH_OUTPUT
    371     : [sbz] "r" (sbz)
    372     : "memory"
    373   );
    374 }
    375 
    376 static inline void arm_cp15_data_cache_invalidate_line(const void *mva)
    377 {
    378   ARM_SWITCH_REGISTERS;
    379 
    380   mva = ARM_CP15_CACHE_PREPARE_MVA(mva);
    381 
    382   asm volatile (
    383     ARM_SWITCH_TO_ARM
    384     "mcr p15, 0, %[mva], c7, c6, 1\n"
    385     ARM_SWITCH_BACK
    386     : ARM_SWITCH_OUTPUT
    387     : [mva] "r" (mva)
    388     : "memory"
    389   );
    390 }
    391 
    392 static inline void arm_cp15_data_cache_invalidate_line_by_set_and_way(uint32_t set_and_way)
    393 {
    394   ARM_SWITCH_REGISTERS;
    395 
    396   asm volatile (
    397     ARM_SWITCH_TO_ARM
    398     "mcr p15, 0, %[set_and_way], c7, c6, 2\n"
    399     ARM_SWITCH_BACK
    400     : ARM_SWITCH_OUTPUT
    401     : [set_and_way] "r" (set_and_way)
    402     : "memory"
    403   );
    404 }
    405 
    406 static inline void arm_cp15_data_cache_clean_line(const void *mva)
    407 {
    408   ARM_SWITCH_REGISTERS;
    409 
    410   mva = ARM_CP15_CACHE_PREPARE_MVA(mva);
    411 
    412   asm volatile (
    413     ARM_SWITCH_TO_ARM
    414     "mcr p15, 0, %[mva], c7, c10, 1\n"
    415     ARM_SWITCH_BACK
    416     : ARM_SWITCH_OUTPUT
    417     : [mva] "r" (mva)
    418     : "memory"
    419   );
    420 }
    421 
    422 static inline void arm_cp15_data_cache_clean_line_by_set_and_way(uint32_t set_and_way)
    423 {
    424   ARM_SWITCH_REGISTERS;
    425 
    426   asm volatile (
    427     ARM_SWITCH_TO_ARM
    428     "mcr p15, 0, %[set_and_way], c7, c10, 2\n"
    429     ARM_SWITCH_BACK
    430     : ARM_SWITCH_OUTPUT
    431     : [set_and_way] "r" (set_and_way)
    432     : "memory"
    433   );
    434 }
    435 
    436 static inline void arm_cp15_data_cache_test_and_clean(void)
    437 {
    438   ARM_SWITCH_REGISTERS;
    439 
    440   asm volatile (
    441     ARM_SWITCH_TO_ARM
    442     "1:\n"
    443     "mrc p15, 0, r15, c7, c10, 3\n"
    444     "bne 1b\n"
    445     ARM_SWITCH_BACK
    446     : ARM_SWITCH_OUTPUT
    447     :
    448     : "memory"
    449   );
    450 }
    451 
    452 static inline void arm_cp15_data_cache_clean_and_invalidate_line(const void *mva)
    453 {
    454   ARM_SWITCH_REGISTERS;
    455 
    456   mva = ARM_CP15_CACHE_PREPARE_MVA(mva);
    457 
    458   asm volatile (
    459     ARM_SWITCH_TO_ARM
    460     "mcr p15, 0, %[mva], c7, c14, 1\n"
    461     ARM_SWITCH_BACK
    462     : ARM_SWITCH_OUTPUT
    463     : [mva] "r" (mva)
    464     : "memory"
    465   );
    466 }
    467 
    468 static inline void arm_cp15_data_cache_clean_and_invalidate_line_by_set_and_way(uint32_t set_and_way)
    469 {
    470   ARM_SWITCH_REGISTERS;
    471 
    472   asm volatile (
    473     ARM_SWITCH_TO_ARM
    474     "mcr p15, 0, %[set_and_way], c7, c14, 2\n"
    475     ARM_SWITCH_BACK
    476     : ARM_SWITCH_OUTPUT
    477     : [set_and_way] "r" (set_and_way)
    478     : "memory"
    479   );
    480 }
    481 
    482 static inline void arm_cp15_data_cache_test_and_clean_and_invalidate(void)
    483 {
    484   ARM_SWITCH_REGISTERS;
    485 
    486   asm volatile (
    487     ARM_SWITCH_TO_ARM
    488     "1:\n"
    489     "mrc p15, 0, r15, c7, c14, 3\n"
    490     "bne 1b\n"
    491     ARM_SWITCH_BACK
    492     : ARM_SWITCH_OUTPUT
    493     :
    494     : "memory"
    495   );
    496 }
    497 
    498 static inline void arm_cp15_drain_write_buffer(void)
    499 {
    500   ARM_SWITCH_REGISTERS;
    501   uint32_t sbz = 0;
    502 
    503   asm volatile (
    504     ARM_SWITCH_TO_ARM
    505     "mcr p15, 0, %[sbz], c7, c10, 4\n"
    506     ARM_SWITCH_BACK
    507     : ARM_SWITCH_OUTPUT
    508     : [sbz] "r" (sbz)
    509     : "memory"
    510   );
    511 }
    512 
    513 static inline void arm_cp15_wait_for_interrupt(void)
    514 {
    515   ARM_SWITCH_REGISTERS;
    516   uint32_t sbz = 0;
    517 
    518   asm volatile (
    519     ARM_SWITCH_TO_ARM
    520     "mcr p15, 0, %[sbz], c7, c0, 4\n"
    521     ARM_SWITCH_BACK
    522     : ARM_SWITCH_OUTPUT
    523     : [sbz] "r" (sbz)
    524     : "memory"
    525   );
    526 }
    527 
    528 #define ARM_CP15_TLB_PREPARE_MVA(mva) \
    529   ((const void *) (((uint32_t) (mva)) & ~0x3fU))
    530313
    531314static inline void arm_cp15_tlb_invalidate(void)
     
    638421}
    639422
     423/** @} */
     424
     425/**
     426 * @name Cache Functions
     427 *
     428 * @{
     429 */
     430
     431static inline uint32_t arm_cp15_get_cache_type(void)
     432{
     433  ARM_SWITCH_REGISTERS;
     434  uint32_t val;
     435
     436  asm volatile (
     437    ARM_SWITCH_TO_ARM
     438    "mrc p15, 0, %[val], c0, c0, 1\n"
     439    ARM_SWITCH_BACK
     440    : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
     441  );
     442
     443  return val;
     444}
     445
     446static inline void arm_cp15_cache_invalidate(void)
     447{
     448  ARM_SWITCH_REGISTERS;
     449  uint32_t sbz = 0;
     450
     451  asm volatile (
     452    ARM_SWITCH_TO_ARM
     453    "mcr p15, 0, %[sbz], c7, c7, 0\n"
     454    ARM_SWITCH_BACK
     455    : ARM_SWITCH_OUTPUT
     456    : [sbz] "r" (sbz)
     457    : "memory"
     458  );
     459}
     460
     461static inline void arm_cp15_instruction_cache_invalidate(void)
     462{
     463  ARM_SWITCH_REGISTERS;
     464  uint32_t sbz = 0;
     465
     466  asm volatile (
     467    ARM_SWITCH_TO_ARM
     468    "mcr p15, 0, %[sbz], c7, c5, 0\n"
     469    ARM_SWITCH_BACK
     470    : ARM_SWITCH_OUTPUT
     471    : [sbz] "r" (sbz)
     472    : "memory"
     473  );
     474}
     475
     476static inline void arm_cp15_instruction_cache_invalidate_line(const void *mva)
     477{
     478  ARM_SWITCH_REGISTERS;
     479
     480  mva = ARM_CP15_CACHE_PREPARE_MVA(mva);
     481
     482  asm volatile (
     483    ARM_SWITCH_TO_ARM
     484    "mcr p15, 0, %[mva], c7, c5, 1\n"
     485    ARM_SWITCH_BACK
     486    : ARM_SWITCH_OUTPUT
     487    : [mva] "r" (mva)
     488    : "memory"
     489  );
     490}
     491
     492static inline void arm_cp15_instruction_cache_invalidate_line_by_set_and_way(uint32_t set_and_way)
     493{
     494  ARM_SWITCH_REGISTERS;
     495
     496  asm volatile (
     497    ARM_SWITCH_TO_ARM
     498    "mcr p15, 0, %[set_and_way], c7, c5, 2\n"
     499    ARM_SWITCH_BACK
     500    : ARM_SWITCH_OUTPUT
     501    : [set_and_way] "r" (set_and_way)
     502    : "memory"
     503  );
     504}
     505
     506static inline void arm_cp15_instruction_cache_prefetch_line(const void *mva)
     507{
     508  ARM_SWITCH_REGISTERS;
     509
     510  mva = ARM_CP15_CACHE_PREPARE_MVA(mva);
     511
     512  asm volatile (
     513    ARM_SWITCH_TO_ARM
     514    "mcr p15, 0, %[mva], c7, c13, 1\n"
     515    ARM_SWITCH_BACK
     516    : ARM_SWITCH_OUTPUT
     517    : [mva] "r" (mva)
     518  );
     519}
     520
     521static inline void arm_cp15_data_cache_invalidate(void)
     522{
     523  ARM_SWITCH_REGISTERS;
     524  uint32_t sbz = 0;
     525
     526  asm volatile (
     527    ARM_SWITCH_TO_ARM
     528    "mcr p15, 0, %[sbz], c7, c6, 0\n"
     529    ARM_SWITCH_BACK
     530    : ARM_SWITCH_OUTPUT
     531    : [sbz] "r" (sbz)
     532    : "memory"
     533  );
     534}
     535
     536static inline void arm_cp15_data_cache_invalidate_line(const void *mva)
     537{
     538  ARM_SWITCH_REGISTERS;
     539
     540  mva = ARM_CP15_CACHE_PREPARE_MVA(mva);
     541
     542  asm volatile (
     543    ARM_SWITCH_TO_ARM
     544    "mcr p15, 0, %[mva], c7, c6, 1\n"
     545    ARM_SWITCH_BACK
     546    : ARM_SWITCH_OUTPUT
     547    : [mva] "r" (mva)
     548    : "memory"
     549  );
     550}
     551
     552static inline void arm_cp15_data_cache_invalidate_line_by_set_and_way(uint32_t set_and_way)
     553{
     554  ARM_SWITCH_REGISTERS;
     555
     556  asm volatile (
     557    ARM_SWITCH_TO_ARM
     558    "mcr p15, 0, %[set_and_way], c7, c6, 2\n"
     559    ARM_SWITCH_BACK
     560    : ARM_SWITCH_OUTPUT
     561    : [set_and_way] "r" (set_and_way)
     562    : "memory"
     563  );
     564}
     565
     566static inline void arm_cp15_data_cache_clean_line(const void *mva)
     567{
     568  ARM_SWITCH_REGISTERS;
     569
     570  mva = ARM_CP15_CACHE_PREPARE_MVA(mva);
     571
     572  asm volatile (
     573    ARM_SWITCH_TO_ARM
     574    "mcr p15, 0, %[mva], c7, c10, 1\n"
     575    ARM_SWITCH_BACK
     576    : ARM_SWITCH_OUTPUT
     577    : [mva] "r" (mva)
     578    : "memory"
     579  );
     580}
     581
     582static inline void arm_cp15_data_cache_clean_line_by_set_and_way(uint32_t set_and_way)
     583{
     584  ARM_SWITCH_REGISTERS;
     585
     586  asm volatile (
     587    ARM_SWITCH_TO_ARM
     588    "mcr p15, 0, %[set_and_way], c7, c10, 2\n"
     589    ARM_SWITCH_BACK
     590    : ARM_SWITCH_OUTPUT
     591    : [set_and_way] "r" (set_and_way)
     592    : "memory"
     593  );
     594}
     595
     596static inline void arm_cp15_data_cache_test_and_clean(void)
     597{
     598  ARM_SWITCH_REGISTERS;
     599
     600  asm volatile (
     601    ARM_SWITCH_TO_ARM
     602    "1:\n"
     603    "mrc p15, 0, r15, c7, c10, 3\n"
     604    "bne 1b\n"
     605    ARM_SWITCH_BACK
     606    : ARM_SWITCH_OUTPUT
     607    :
     608    : "memory"
     609  );
     610}
     611
     612static inline void arm_cp15_data_cache_clean_and_invalidate_line(const void *mva)
     613{
     614  ARM_SWITCH_REGISTERS;
     615
     616  mva = ARM_CP15_CACHE_PREPARE_MVA(mva);
     617
     618  asm volatile (
     619    ARM_SWITCH_TO_ARM
     620    "mcr p15, 0, %[mva], c7, c14, 1\n"
     621    ARM_SWITCH_BACK
     622    : ARM_SWITCH_OUTPUT
     623    : [mva] "r" (mva)
     624    : "memory"
     625  );
     626}
     627
     628static inline void arm_cp15_data_cache_clean_and_invalidate_line_by_set_and_way(uint32_t set_and_way)
     629{
     630  ARM_SWITCH_REGISTERS;
     631
     632  asm volatile (
     633    ARM_SWITCH_TO_ARM
     634    "mcr p15, 0, %[set_and_way], c7, c14, 2\n"
     635    ARM_SWITCH_BACK
     636    : ARM_SWITCH_OUTPUT
     637    : [set_and_way] "r" (set_and_way)
     638    : "memory"
     639  );
     640}
     641
     642static inline void arm_cp15_data_cache_test_and_clean_and_invalidate(void)
     643{
     644  ARM_SWITCH_REGISTERS;
     645
     646  asm volatile (
     647    ARM_SWITCH_TO_ARM
     648    "1:\n"
     649    "mrc p15, 0, r15, c7, c14, 3\n"
     650    "bne 1b\n"
     651    ARM_SWITCH_BACK
     652    : ARM_SWITCH_OUTPUT
     653    :
     654    : "memory"
     655  );
     656}
     657
     658/** @} */
     659
     660static inline void arm_cp15_drain_write_buffer(void)
     661{
     662  ARM_SWITCH_REGISTERS;
     663  uint32_t sbz = 0;
     664
     665  asm volatile (
     666    ARM_SWITCH_TO_ARM
     667    "mcr p15, 0, %[sbz], c7, c10, 4\n"
     668    ARM_SWITCH_BACK
     669    : ARM_SWITCH_OUTPUT
     670    : [sbz] "r" (sbz)
     671    : "memory"
     672  );
     673}
     674
     675static inline void arm_cp15_wait_for_interrupt(void)
     676{
     677  ARM_SWITCH_REGISTERS;
     678  uint32_t sbz = 0;
     679
     680  asm volatile (
     681    ARM_SWITCH_TO_ARM
     682    "mcr p15, 0, %[sbz], c7, c0, 4\n"
     683    ARM_SWITCH_BACK
     684    : ARM_SWITCH_OUTPUT
     685    : [sbz] "r" (sbz)
     686    : "memory"
     687  );
     688}
     689
     690/** @} */
     691
    640692#ifdef __cplusplus
    641693}
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