Index: cpukit/score/cpu/mips/ChangeLog
===================================================================
--- cpukit/score/cpu/mips/ChangeLog	(revision a68128530cc39e10ef29c20c17f2e30900921b27)
+++ cpukit/score/cpu/mips/ChangeLog	(revision 5e39823b3fe8bb98bf6c9c114752cd21f2bed7bc)
@@ -1,37 +1,20 @@
-2002-07-26	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
-	* Makefile.am: Build libscorecpu.a instead of rtems-cpu.rel.
-
-2002-07-22	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
-	* Makefile.am: Use .$(OBJEXT) instead of .o.
-
-2002-07-16      Greg Menke <gregory.menke@gsfc.nasa.gov>
-
+2002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
+
+	* cpu_asm.S: Clarified some comments, removed code that forced
+	SR_IEP on when returning from an interrupt.
+
+2002-06-27	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
+
+	* configure.ac: Add RTEMS_PROG_CCAS
+
+2002-06-27	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
+
+	* configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
+	Add AC_PROG_RANLIB.
+
+2002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
 	* cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
 	deadlock caused by interrupt arriving while dispatching.
-
-2002-07-05	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
-	* configure.ac: RTEMS_TOP(../../../..).
-
-2002-07-03	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
-	* rtems.c: Remove.
-	* Makefile.am: Reflect changes above.
-
-2002-07-01	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
-	* configure.ac: Remove RTEMS_PROJECT_ROOT.
-
-2002-06-27	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
-	* configure.ac: Add RTEMS_PROG_CCAS
-
-2002-06-27	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
-	* configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
-	Add AC_PROG_RANLIB.
-
+	
 2002-06-17	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
 
Index: cpukit/score/cpu/mips/cpu_asm.S
===================================================================
--- cpukit/score/cpu/mips/cpu_asm.S	(revision a68128530cc39e10ef29c20c17f2e30900921b27)
+++ cpukit/score/cpu/mips/cpu_asm.S	(revision 5e39823b3fe8bb98bf6c9c114752cd21f2bed7bc)
@@ -394,7 +394,7 @@
 	/* 
 	** this code grabs the userspace EPC if we're dispatching from
-	** an interrupt frame or fakes an address as the EPC if we're
-	** not.  This is for the gdbstub's benefit so it can know
-	**  where each thread is running.
+	** an interrupt frame or supplies the address of the dispatch
+	** routines if not.  This is entirely for the gdbstub's benefit so 
+	** it can know where each task is running.
 	**
 	** Its value is only set when calling threadDispatch from
@@ -455,12 +455,12 @@
 
 /*
-** Incorporate the new task's FP coprocessor state and interrupt mask/enable
+** Incorporate the incoming task's FP coprocessor state and interrupt mask/enable
 ** into the status register.  We jump thru the requisite hoops to ensure we 
 ** maintain all other SR bits as global values.
 **
-** Get the thread's FPU enable, int mask & int enable bits.  Although we keep the 
+** Get the task's FPU enable, int mask & int enable bits.  Although we keep the 
 ** software int enables on a per-task basis, the rtems_task_create
 ** Interrupt Level & int level manipulation functions cannot enable/disable them, 
-** so they are automatically enabled for all tasks.  To turn them off, a thread  
+** so they are automatically enabled for all tasks.  To turn them off, a task  
 ** must itself manipulate the SR register.  
 **
@@ -471,5 +471,5 @@
 ** of that task's SR bits, as seen in cpu.c
 **
-** Note, interrupts are disabled before context is saved, though the thread's
+** Note, interrupts are disabled before context is saved, though the task's
 ** interrupt enable state is recorded.  The task swapping in will apply its
 ** specific SR bits, including interrupt enable.  If further task-specific
@@ -485,5 +485,12 @@
 	or	t2,SR_EXL + SR_IE
 #elif __mips == 1
-	or	t2,SR_IEC + SR_IEP + SR_IEO	/* save current & previous int enable */
+	/* 
+	** Save current, previous & old int enables.  This is key because
+	** we can dispatch from within the stack frame used by an
+	** interrupt service.  The int enables nest, but not beyond
+	** previous and old because of the dispatch interlock seen
+	** in the interrupt processing code
+	*/
+	or	t2,SR_IEC + SR_IEP + SR_IEO
 #endif
 	and	t0,t2		/* keep only the per-task bits */
@@ -646,9 +653,4 @@
 _ISR_Handler_Exception:
 
-	/*
-	sw	t0,0x8001FF00
-	sw	t1,0x8001FF04
-	*/
-	
 	/*  If we return from the exception, it is assumed nothing
          *  bad is going on and we can continue to run normally.
@@ -720,9 +722,14 @@
 	** It is expected the only code using the exception processing is
 	** either the gdb stub or some user code which is either going to
-	** panic or do something useful.
+	** panic or do something useful.  Regardless, it is up to each
+	** exception routine to properly adjust EPC, so the code below
+	** may be helpful for doing just that.
 	*/
-
 	
 /* *********************************************************************
+** this code follows the R3000's exception return logic, but is not
+** needed because the gdb stub does it for us.  It might be useful
+** for something else at some point...
+**
 	* compute the address of the instruction we'll return to *
 
@@ -803,4 +810,12 @@
         /* do NOT restore the cause as this could mess up the world */
 
+	/* 
+	** Jump all the way out.  If theres a pending interrupt, just
+	** let it be serviced later.  Since we're probably using the 
+	** gdb stub, we've already disrupted the ISR service timing
+	** anyhow.  We oughtn't mix exception and interrupt processing
+	** in the same exception call in case the exception stuff
+	** might interfere with the dispatching & timer ticks.
+	*/
 	j	 _ISR_Handler_exit
 	NOP
@@ -960,9 +975,14 @@
 
 #if __mips == 1
-	/* make sure previous int enable is on  because we're returning from an interrupt
+	/* disabled 7/29, gregm, this tasks context was saved previously in an interrupt,
+	** so we'll just restore the task's previous interrupt enables.
+
+	**
+	** make sure previous int enable is on  because we're returning from an interrupt
 	** which means interrupts have to be enabled
-	*/
+	
 	li	t1,SR_IEP
 	or	t0,t1
+	*/
 #endif
         MTC0    t0, C0_SR
