Changeset 5e39823 in rtems


Ignore:
Timestamp:
Aug 14, 2002, 10:59:05 PM (18 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
8e0738e1
Parents:
a681285
Message:

2002-08-14 Greg Menke <gregory.menke@…>

  • cpu_asm.S: Clarified some comments, removed code that forced SR_IEP on when returning from an interrupt.
Location:
cpukit/score/cpu/mips
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/mips/ChangeLog

    ra681285 r5e39823  
    1 2002-07-26      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    2 
    3         * Makefile.am: Build libscorecpu.a instead of rtems-cpu.rel.
    4 
    5 2002-07-22      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    6 
    7         * Makefile.am: Use .$(OBJEXT) instead of .o.
    8 
    9 2002-07-16      Greg Menke <gregory.menke@gsfc.nasa.gov>
    10 
     12002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
     2
     3        * cpu_asm.S: Clarified some comments, removed code that forced
     4        SR_IEP on when returning from an interrupt.
     5
     62002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
     7
     8        * configure.ac: Add RTEMS_PROG_CCAS
     9
     102002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
     11
     12        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
     13        Add AC_PROG_RANLIB.
     14
     152002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
    1116        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
    1217        deadlock caused by interrupt arriving while dispatching.
    13 
    14 2002-07-05      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    15 
    16         * configure.ac: RTEMS_TOP(../../../..).
    17 
    18 2002-07-03      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    19 
    20         * rtems.c: Remove.
    21         * Makefile.am: Reflect changes above.
    22 
    23 2002-07-01      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    24 
    25         * configure.ac: Remove RTEMS_PROJECT_ROOT.
    26 
    27 2002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    28 
    29         * configure.ac: Add RTEMS_PROG_CCAS
    30 
    31 2002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    32 
    33         * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
    34         Add AC_PROG_RANLIB.
    35 
     18       
    36192002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    3720
  • cpukit/score/cpu/mips/cpu_asm.S

    ra681285 r5e39823  
    394394        /*
    395395        ** this code grabs the userspace EPC if we're dispatching from
    396         ** an interrupt frame or fakes an address as the EPC if we're
    397         ** not.  This is for the gdbstub's benefit so it can know
    398         **  where each thread is running.
     396        ** an interrupt frame or supplies the address of the dispatch
     397        ** routines if not.  This is entirely for the gdbstub's benefit so
     398        ** it can know where each task is running.
    399399        **
    400400        ** Its value is only set when calling threadDispatch from
     
    455455
    456456/*
    457 ** Incorporate the new task's FP coprocessor state and interrupt mask/enable
     457** Incorporate the incoming task's FP coprocessor state and interrupt mask/enable
    458458** into the status register.  We jump thru the requisite hoops to ensure we
    459459** maintain all other SR bits as global values.
    460460**
    461 ** Get the thread's FPU enable, int mask & int enable bits.  Although we keep the
     461** Get the task's FPU enable, int mask & int enable bits.  Although we keep the
    462462** software int enables on a per-task basis, the rtems_task_create
    463463** Interrupt Level & int level manipulation functions cannot enable/disable them,
    464 ** so they are automatically enabled for all tasks.  To turn them off, a thread 
     464** so they are automatically enabled for all tasks.  To turn them off, a task 
    465465** must itself manipulate the SR register. 
    466466**
     
    471471** of that task's SR bits, as seen in cpu.c
    472472**
    473 ** Note, interrupts are disabled before context is saved, though the thread's
     473** Note, interrupts are disabled before context is saved, though the task's
    474474** interrupt enable state is recorded.  The task swapping in will apply its
    475475** specific SR bits, including interrupt enable.  If further task-specific
     
    485485        or      t2,SR_EXL + SR_IE
    486486#elif __mips == 1
    487         or      t2,SR_IEC + SR_IEP + SR_IEO     /* save current & previous int enable */
     487        /*
     488        ** Save current, previous & old int enables.  This is key because
     489        ** we can dispatch from within the stack frame used by an
     490        ** interrupt service.  The int enables nest, but not beyond
     491        ** previous and old because of the dispatch interlock seen
     492        ** in the interrupt processing code
     493        */
     494        or      t2,SR_IEC + SR_IEP + SR_IEO
    488495#endif
    489496        and     t0,t2           /* keep only the per-task bits */
     
    646653_ISR_Handler_Exception:
    647654
    648         /*
    649         sw      t0,0x8001FF00
    650         sw      t1,0x8001FF04
    651         */
    652        
    653655        /*  If we return from the exception, it is assumed nothing
    654656         *  bad is going on and we can continue to run normally.
     
    720722        ** It is expected the only code using the exception processing is
    721723        ** either the gdb stub or some user code which is either going to
    722         ** panic or do something useful.
     724        ** panic or do something useful.  Regardless, it is up to each
     725        ** exception routine to properly adjust EPC, so the code below
     726        ** may be helpful for doing just that.
    723727        */
    724 
    725728       
    726729/* *********************************************************************
     730** this code follows the R3000's exception return logic, but is not
     731** needed because the gdb stub does it for us.  It might be useful
     732** for something else at some point...
     733**
    727734        * compute the address of the instruction we'll return to *
    728735
     
    803810        /* do NOT restore the cause as this could mess up the world */
    804811
     812        /*
     813        ** Jump all the way out.  If theres a pending interrupt, just
     814        ** let it be serviced later.  Since we're probably using the
     815        ** gdb stub, we've already disrupted the ISR service timing
     816        ** anyhow.  We oughtn't mix exception and interrupt processing
     817        ** in the same exception call in case the exception stuff
     818        ** might interfere with the dispatching & timer ticks.
     819        */
    805820        j        _ISR_Handler_exit
    806821        NOP
     
    960975
    961976#if __mips == 1
    962         /* make sure previous int enable is on  because we're returning from an interrupt
     977        /* disabled 7/29, gregm, this tasks context was saved previously in an interrupt,
     978        ** so we'll just restore the task's previous interrupt enables.
     979
     980        **
     981        ** make sure previous int enable is on  because we're returning from an interrupt
    963982        ** which means interrupts have to be enabled
    964         */
     983       
    965984        li      t1,SR_IEP
    966985        or      t0,t1
     986        */
    967987#endif
    968988        MTC0    t0, C0_SR
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